High temperature Silicon Carbide (SiC) integrated circuit (IC) processes have enabled devices that operate at >450°C for more than a year. These results have established the need for more advanced and practical packaging strategies. Off the shelf state of the art packages cannot withstand the same high temperatures as the semiconductor can for long periods of time. Packaging SiC die to survive temperatures >450°C, while also maintaining a reasonable packaging strategy that is agile, rapid, and modular, presents new challenges. Presented is a technique for packaging SiC die with a focus on additive manufacturing, modular design scaling, and rugged survivability. This packaging strategy utilizes state of the art Additive Manufacturing (AM) methods, using an nScrypt 3Dn-Tabletop printer, together with stereolithography (SLA) digital light processing (DLP) 3D printing. Ultra-violet (UV) curable ceramic resins are used to create high temperature connectors. A design environment is also described, in which first time correct, interconnect layers are verified in software to reduce the risk of errors. A Ceramic Wiring Board Process Design Kit (CWBPDK) allows the design of single or multiple layers of metal, with fabricated SiC die. This interconnect is verified with standard design rule checking (DRC) and layout vs. schematic (LVS) software. Entire systems in packages can be verified using multiple SiC die. Input and output pins (I/O) are connected to these modules using metal connectors. After design, manufacturing can be performed in just a few days. A system in package for driving a stepper motor was designed and fabricated using this packaging method. The motor actuator design utilizes four separate SiC die. These die contain large JFETs designed for sourcing current in a unipolar stepper motor architecture. This module was placed in a furnace at 470°C and demonstrated functional operation for over 1000 hours. These devices were able to source an average of 30 mA in >400°C temperatures to drive the room temperature stepper motor. A high I/O count, next generation package for discrete SiC chips was also designed using this packaging system. A single large JFET component was soaked for over 100 hours at both 500°C and 800°C. Utilizing Ozark IC’s automated test design environment, several DC and transient variables were captured for both tests and will be presented.
In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.
Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design have enabled the ability to design complex, dense, digital blocks. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC, too costly and risky. For large scale integrated digital circuits, computer aided design (CAD) tools are necessary, specifically the use of automatic synthesis, rule-based placement and signal routing software. The tools are used in progression as a design flow and are necessary for the timely and accurate creation of high-density digital designs. Application of an automated digital design flow to high-temperature SiC processes presents new challenges, such as extraction of timing characteristics at high temperatures, specifically above 400°C, as well as managing the complexity of synthesis, optimization of cell placement, verification of timing enclosure, and identifying routing constraints. These activities all require a willingness to extend and enhance the CAD software. Presented is a high temperature SiC digital synthesis flow. This flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. A digital controller for a 10,000-pixel UV focal plan array (FPA) in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a finite state machine (FSM), that monitors several counters, shift registers and combinational logic feedback signals. The FSM is configured to optimize the FPA for different applications and exposures. The Register-Transfer Level (RTL) design of the FSM produces between 900 and 1,000 gates, depending on the temperature-dependent time closure with a total footprint of 14mm2. Typical SiC processes present a non-monotonic clock speed over temperature. The advantage of this digital design flow is that it allows the designer to target a temperature corner for the netlist design but verify its operation over a > 400°C operating range. This flow is currently being enhanced for use with NASA's SiC JFET-R process to create a high temperature communication protocol interface.
The need for digital control and observability is continuing to expand into inhospitable environments - engines, energy exploration systems and space exploration. The limited available selection of components to fabricate modules for these high temperature environments, both active and passive, force manufacturers into packaging compromises that limit the performance and reliability of these modules. The lack of selection, as well as ordering requirements, dramatically slows prototyping cycles and the creation of solutions. Production of thermally hardened active and passive components that are designed and fabricated with packaging in mind can extend the operating temperature range of heterogeneously integrated systems. Ozark IC has demonstrated a wire bonding process that shows reliable powered function of a heterogeneously integrated system at 200°C for over 7500 hours. Ozark IC has also tested modules packaged with homogeneous gold metallization that endure powered function at 800°C for 1 to 50 hours, and powered function at 500°C for more than 100 hours. Increasing the availability of newly manufactured semiconductor die and passive components with compatible metallization would enable these high temperature packaging methods to rapidly advance the state of the art for thermally hardened electronics systems. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.
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