Security now constitutes a big concern for a day & is rising fast every day. Save your house, records, money & other valuable things like jewellery is vital to all. The methodologies used by offenders have now strengthened with the advancement of very recent technology. Therefore, the appropriate monitoring strategies for global transformation are very critical to develop. Video detection and tracking system are the latest and powerful technologies used against burglary and stealing. However, some individuals can not bear the cost of building and running such devices. A new and efficient system has been suggested for motion detection rather than applying different complex algorithms. When the PIR sensor senses the action, it records the image with the camera & sends it to the user. The cost of construction can be that, and the energy-efficient program can be used with this approach.
FIR filters, microprocessor and digital signal processor are the core system of multipliers. MAC is the most important building block in DSP system. The key element of high throughput multiplier and accumulator unit (MAC) is to achieve a high-performance digital signal processing application. In this paper, Modified Russian Peasant Multiplier (MRPM) using Ripple Carry Adder (RCA) has been proposed. According to Russian Rule"s, Divide and conquer technique is used in the multiplication process. But, in perspective of digital design, only shifters and adders are used in Russian Peasant Multiplier to produce Partial Product Generation (PPG). A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage. Here, ripple carry adder is used for low power application. Reducing the chip size, increasing the speed and reducing the power consumption are main crucial factors in VLSI System design environment. The goal of this research work is to design the VLSI implementation of MAC for high-speed DSP applications. For designing the Multiplication and accumulation unit, different kinds of multipliers and adders are considered in this paper. The total operation is coded with Verilog HDL using ModelSim 6.3C, synthesized by using Xilinx ISE 12.4i design tool.
Improvement of Digital FIR filter is vital role in the field of Digital SignalProcessing in order to reduce the area, delay and power. MAC (Multiplication and Accumulation) unit of Finite Impulse Response (FIR) filter has been designed using efficient Multiplier and adder circuits for Optimized APT (Area, Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. This compact Full adder and half adder structures are incorporated into reduced Wallace Multiplier and improved Carry look-ahead Adder. Reduced Wallace tree multiplier and enhanced carry lookahead adder for digital FIR filter has been proposed in this paper. The proposed 16-bit Carry look-ahead adder has been improved. Consequently the delay of enhanced Carry look ahead Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization. Simulation results are done by using Modelsim 6.3C and synthesized by Xilinx ISE 10.1i design tool.
A design of reconfigurable architecture of FIR filter has been implemented using a Least Mean Square (LMS) adaptive filter. LMS adaptive filter is mainly sued for reducing the coefficients of the filter. Generally, a LMS filter contains normal adder, subtractor, mixer and a delay part.
Most of the concepts deal with an adder namely Full Adder (FA), Ripple Carry Adder (RCA), Carry Select Adder (CSLA), etc., Instead of using CSLA; Borrow Select Subtractor (BSLS) is used in LMS filter architecture. By using BSLA LMS adaptive filter in a reconfigurable FIR filter architecture
in the proposed scheme, the area, power and delay will be reduced. The proposed scheme achieves better performance when compared to an existing scheme. The proposed method is implemented in ModelSim tool and efficiency has been calculated by using the device Virtex 6 Low Power in Xilinx ISE
Design Suite 12.4.
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