Reduced Complexity Wallace Tree Mulplier and Enhanced Carry Look-Ahead Adder for Digital FIR Filter 

Abstract

Improvement of Digital FIR filter is vital role in the field of Digital SignalProcessing in order to reduce the area, delay and power. MAC (Multiplication and Accumulation) unit of Finite Impulse Response (FIR) filter has been designed using efficient Multiplier and adder circuits for Optimized APT (Area, Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. This compact Full adder and half adder structures are incorporated into reduced Wallace Multiplier and improved Carry look-ahead Adder. Reduced Wallace tree multiplier and enhanced carry lookahead adder for digital FIR filter has been proposed in this paper. The proposed 16-bit Carry look-ahead adder has been improved. Consequently the delay of enhanced Carry look ahead Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization. Simulation results are done by using Modelsim 6.3C and synthesized by Xilinx ISE 10.1i design tool.

Low power and area efficient design of fir filter using enhanced clock gating technique

“…Where, u(k) is the impulse response with weight factor k. The performance speed of the FIR filter is realized with the multiplier logic model and the number of used adder logic improves the performance of the multiplier and the filter. The carry look-ahead logic is the high-speed adder logic, which improves the performance of adder by calculating with the values of carry bits [11] to [13]. Vraious parallel prefix adders are reviewed in [14] to [15].…”