Highly optimised reconfigurable hardware architecture is proposed of 64 bit block ciphers MISTY1 and KASUMI for wide-area cryptographic applications. The reconfigurable hardware architecture is comprised of reconfigurable components consisting of FL function, FO/FI function and XOR function designed to perform MISTY1 and KASUMI algorithms round transformation functions. In addition, reconfigurable FO/FI function is adequate to generate MISTY1 extended keys for onward use in MISTY1 round transformation function. The substitution functions S9 and S7 for MISTY1 and KASUMI algorithms are optimised for area and throughput. Common subexpression elimination for AND-XOR logic combined with permutation/combination technique for AND gates reduces the area considerably, whereas parallel execution improves the throughput. With this design approach, application specific integrated circuit (ASIC) implementations using Synopsys Design Complier, SMIC 0.18 µm at 1.8 V achieved an area of 3481 NAND gates having throughput of 130.2 and 154.56 Mbits/s for MISTY1 and KASUMI, respectively. Synthesised FPGA implementation using Xilinx Artix 7 FPGA yielded an area of 487 configurable logic block (CLB) Slices having throughput of 209.43 and 248.7 Mbits/s for MISTY1 and KASUMI, respectively. Detailed design and performance analysis of reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI for ASIC implementations is described.

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Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.

Differential power analysis (DPA) is an effective side channel attack method, which poses a critical threat to cryptographic algorithms, especially lightweight ciphers such as SIMON. In this paper, we propose an area-efficient countermeasure against DPA on SIMON based on the power randomization. Firstly, we review and analyze the architecture of SIMON algorithm. Secondly, we prove the threat of DPA attack to SIMON by launching actual DPA attack on SIMON 32/64 circuit. Thirdly, a low-cost power randomization scheme is proposed by combining fault injection with double rate technology, and the corresponding circuit design is implemented. To the best of our knowledge, this is the first scheme that applies the combination of fault injection and double rate technology to the DPA-resistance. Finally, the t-test is used to evaluate the security mechanism of the proposed designs with leakage quantification. Our experimental results show that the proposed design implements DPA-resistance of SIMON algorithm at certain overhead the cost of 47.7% LUTs utilization and 39.6% registers consumption. As compared to threshold implementation and bool mask, the proposed scheme has greater advantages in resource consumption.

Optical networks on chip (ONoC) delivers a promising alternative to meet growing needs of higher bandwidth and low power consumption in manycore processors. Optical routers are the key element in ONoCs that significantly affect the performance of overall network. In this letter, we propose a rearrangeable non-blocking 6 × 6 router (RoR) constructed with 2 × 2 hybrid photonic-plasmonic switching (HPPS) elements. Router architectures with 15 HPPS elements and an optimized design using reduced HPPS elements are presented and analyzed. In optimized form, proposed design consumes only 12 HPPS elements which results in low insertion loss and crosstalk noise in comparison to the unoptimized architecture. We observe up to 50% reduction in switching elements count in comparison to other router architecture of same radix.

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In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for areaconstrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for s-boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date.

Optical network-on-chip is considered to be a promising technology to solve the problems of low bandwidth and high latency in the traditional interconnection network. However, due to the inevitable leakage of optical devices, the optical signal will receive crosstalk noise during transmission. In this paper, a heuristic fusion mapping algorithm PSO_SA for crosstalk optimization is proposed. First, the initial optimal mapping is obtained by particle swarm optimization, and then the local optimization of the mapping scheme is removed by combining with simulated annealing algorithm. The experimental results show that the crosstalk optimization performance of PSO_SA algorithm is better than that of GA algorithm in 263 dec, Wavelet, DVOPD and other applications, and the maximum optimization degree is 28.7%.