Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Abstract

In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for areaconstrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for s-boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date.

On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers

“…Thus, the entire bit-stream and logic functionality / selection methodology has to be uploaded on the initial-run of FPGA and is, therefore, more prone to attacks. Moreover, the repetitive-loop structure results in a low throughput value of 130.2 Mbps and in-turn the high-power consumption [ 15 – 26 ]. Studies on static reconfigurable cryptographic modules have also been proposed for SNOW / ZUC algorithms and AES / KASUMI / SNOW / ZUC algorithms signifying flexible implementations [ 14 , 27 – 36 ].…”

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

“…To meet the requirement of the Internet of ings, cryptographic algorithms are frequently optimized for area reduction and high throughput implementation or to achieve a good tradeoff between throughput and speed [12][13][14][15][16][17][18][19][20][21][22][23][24][25]. For low-area design, reutilization/logic optimization methodologies have been widely adopted thereby implementing s-boxes using combinational logic [12][13][14][15][16][17][18][19][20]. A single-round MISTY1 architecture designed for compact implementation is proposed in [20] consisting of only oddround functions, i.e., 2 × FL functions, 1 × FO function, and 1 × 32 bit XOR.…”

“…Finally, 2 × area-efficient MISTY1 design schemes are proposed in [17] based on the combined substitution unit and threshold throughput requirements.…”