RoR: A low insertion loss design of rearrangeable hybrid photonic-plasmonic 6 × 6 non-blocking router for ONoCs

Yahya, Muhammad Rehan; Wu, Ning; Gao, Yan; Feng, Guorui; Ahmed, Tanveer

doi:10.1587/elex.16.20190346

Cited by 8 publications

(3 citation statements)

References 30 publications

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“…On-chip optical interconnects have appeared as a concrete alternative to the ENoCs. The optical interconnects are compatible with complementary metal oxide semiconductor (CMOS) technology that makes them highly appropriate to deploy as on-chip interconnects [5][6].…”

Section: Introductionmentioning

confidence: 99%

Optimized 6x6 Optical Router for Three Dimensional Optical Networks-on-Chip

Jadhav¹,

Chaudhari²

2022

J. Phys.: Conf. Ser.

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The interconnection network is very influential in Multiprocessor system-on-chip (MPSoC) performance. Due to low power efficiency and high latency, conventional interconnects are replaced by electrical networks on-chip (ENoC). However, ENoCs cannot gratify the bandwidth, latency and loss requirements within the available power budget of optical integrated circuits. The reasons being restricted bandwidth, extended delay, and reasonably high power consumption. So, ENoC are being replaced by optical networks-on-chip (ONoC). ONoC has emerged as a promising substitute to provide greater bandwidth, low latency and low power ingestion in MPSoCs. Number of cores required on-chip is increasing which leads to demand of multilayer multi-core processors. Three dimensional (3D) ONoC has become essential for such multilayer multi-core processors. For 3D ONoC, in this paper we have proposed 6x6 non-blocking optical router using micro-ring resonator (MRR) with less number of waveguide crossings and waveguide bendings. Phoenix software is used to simulate proposed optical router. Insertion loss of proposed optical router is lowest among existing non-blocking optical routers of 3D ONoC.

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Section: Introductionmentioning

confidence: 99%

Optimized 6x6 Optical Router for Three Dimensional Optical Networks-on-Chip

Jadhav¹,

Chaudhari²

2022

J. Phys.: Conf. Ser.

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“…The on-chip optical communication using waveguides as the transmission medium has essential advantages compared to traditional electrical communication [1][2][3][4]. The characteristics of low delay, high bandwidth, and low power consumption can effectively solve the ongoing bottlenecks of on-chip communication [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping

Feng

2020

IEICE Electron. Express

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Wavelength division multiplexing (WDM) mesh-based optical network on chip (ONoC) have recently received considerable attention due to their regular topology and higher throughput. However, available wavelengths are finite resources. Thus, to minimize the number of wavelengths, this letter proposes an efficient WDM mesh-based ONoC mapping approach, which is based on a particle swarm optimization algorithm. Experimental results reveal that our proposal has a positive effect in minimizing the number of wavelengths needed compared to random mapping. The tradeoff between the number of wavelengths and the network size is also investigated, and it is found that increasing the network size can reduce the number of wavelengths needed. Meanwhile, the experiments show that the structure has better network performance and less communication resource utilization.

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“…Cluster-based topology saves chip area and requires a 6-port optical router for the additional core connected to the same router. Different 6-port optical switch/router designs have been proposed to fulfill the requirements of cluster Mesh ONoCs [35][36][37].…”

Section: Introductionmentioning

confidence: 99%

HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

Yahya

Gao

et al. 2019

Electronics

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Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.

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RoR: A low insertion loss design of rearrangeable hybrid photonic-plasmonic 6 × 6 non-blocking router for ONoCs

Cited by 8 publications

References 30 publications

Optimized 6x6 Optical Router for Three Dimensional Optical Networks-on-Chip

Optimized 6x6 Optical Router for Three Dimensional Optical Networks-on-Chip

Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping

HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

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