No abstract

High power densities lead to thermal hot spots in modern processors. These power densities are expected to reach kW/cm 2 scale in future high-performance chips and this increase may significantly degrade performance and reliability, if not handled efficiently. Using two-phase vapor chambers (VCs) with micropillar wick evaporators is an emerging technique that removes heat through the evaporation process of a coolant and has the potential to remove high heat fluxes. In this cooling system, the coolant is supplied passively to the micropillar wick via capillary pumping, eliminating the need for an external pump and ensuring stable thinfilm flow. Evaluation of such an emerging cooling technique on realistic chip power densities and micropillar geometries necessitates accurate and fast thermal models. Although multiphysics simulators based on either finite-element or finitevolume methods are highly accurate, they have long design and simulation times. This paper introduces a novel compact thermal model capable of simulating two-phase vapor chambers with micropillar wick evaporators. In comparison to COMSOL, our model shows a competitively low error of 1.25 • C and a 214x speedup. We also present a comparison of the cooling performance of different cooling techniques such as a conventional heat sink, liquid cooling via microchannels, hybrid cooling using thermoelectric coolers and liquid cooling via microchannels, and two-phase VCs with micropillar wick evaporators for the first time. Based on our observations, twophase VCs and microchannel-based two-phase cooling show better cooling performance for hot spot power densities of less than 1500 W/cm 2 , while hybrid cooling achieves lower hot spot temperature and thermal gradients for hot spot power densities between 1500 and 2000 W/cm 2 .

No abstract

No abstract

Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs manage communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing where hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router's local core. Such a utilization-centric design approach can raise security issues in MPSoCs-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

No abstract

No abstract

No abstract