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After the successful development of JPEG2000, many state-of-art wavelet-based image coding algorithms have been developed. However, the traditional discrete wavelet transform (DWT) is implemented with memory intensive and time consuming algorithms and therefore has very high system resource requirements. In particular, the very large required memory poses a serious limitation for multimedia applications on memory-constrained portable devices, such as digital cameras and sensor nodes. In this paper, we propose a novel wavelet-based image coder with low memory requirements and low complexity that preserves the compression efficiency. Our encoder employs the Fractional Wavelet Filter (FrWF) to calculate the DWT coefficients, which are quantized and encoded with a novel Low Memory Block Tree Coding (LMBTC) algorithm. LMBTC is a listless form of the Wavelet Block Tree Coding (WBTC) algorithm. Simulation results demonstrate that the proposed coder significantly reduces memory requirements and computational complexity and has competitive coding efficiency in comparison with other state-of-art coders. FrWF combined with LMBTC is thus a viable option for image communication over wireless sensor networks.Index Terms-Fractional wavelet filter, Low memory image codec, Visual sensors, Wireless sensor networks.

This paper proposes a novel algorithm to compute the 2-D discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost visual sensor and Internet of Things (IoT) nodes. The main advantages of the proposed segmented modified fractional wavelet filter (SMFrWF) are reduced computation (time) complexity and energy consumption compared to the state-of-the-art low-memory 2-D DWT computation methods. In particular, the conventional convolution-based DWT is very fast but requires large random access memory (RAM), as the entire image needs to be in the system memory. The fractional wavelet filter (FrWF) requires only a small RAM but has high complexity due to multiple readings of image lines. The proposed SMFrWF avoids the multiple readings of image lines, thus reducing the memory read access time and, thereby, the complexity. We evaluated the proposed SMFrWF through MATLAB simulations with 70 popular gray-scale test images of dimensions ranging from 256×256 up to 8192×8192 pixels. The results show that for images of size 2048 × 2048 pixels, the proposed SMFrWF (with four segments per line) has 16.8% and 53.6% lower time complexities than the conventional DWT and FrWF, respectively. The proposed SMFrWF has also been modeled in a hardware description language (HDL) and implemented on an Artix-7 field-programmable gate array (FPGA) platform to evaluate the hardware performance. We observed that the proposed SMFrWF has 65% lower energy consumption than the FrWF (both implemented on the same board). Thus, the proposed SMFrWF appears suitable for computing the wavelet transform coefficients of HR images on low-cost visual sensors and IoT platforms.INDEX TERMS Discrete wavelet transform (DWT), low memory, low complexity, low-cost portable devices, visual sensors.

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This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on lowcost memory-constrained sensor nodes used in visual sensor networks (VSN) or Internet of Multimedia Things (IoMT). The main feature of the proposed architecture is the novel data scanning technique that makes memory requirement independent of the image size. The proposed architecture needs only (30S) words of memory, where S is the number of parallel processing units and a critical path delay (CPD) equal to the delay of a multiplier (T m ). Furthermore, a multiplierless version of this architecture is also proposed which reduces the CPD to T a

This paper proposes and evaluates the LFrWF, a novel lifting-based architecture to compute the discrete wavelet transform (DWT) of images using the fractional wavelet filter (FrWF). In order to reduce the memory requirement of the proposed architecture, only one image line is read into a buffer at a time. Aside from an LFrWF version with multipliers, i.e., the LFr WF m , we develop a multiplier-less LFrWF version, i.e., the LFr WF ml , which reduces the critical path delay (CPD) to the delay T a of an adder. The proposed LFr WF m and LFr WF ml architectures are compared in terms of the required adders, multipliers, memory, and critical path delay with state-of-the-art DWT architectures. Moreover, the proposed LFr WF m and LFr WF ml architectures, along with the state-of-the-art FrWF architectures (with multipliers (Fr WF m ) and without multipliers (Fr WF ml )) are compared through implementation on the same FPGA board. The LFr WF m requires 22% less look-up tables (LUT), 34% less flip-flops (FF), and 50% less compute cycles (CC) and consumes 65% less energy than the Fr WF m . Also, the proposed LFr WF ml architecture requires 50% less CC and consumes 43% less energy than the Fr WF ml . Thus, the proposed LFr WF m and LFr WF ml architectures appear suitable for computing the DWT of images on wearable sensors.

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