Summary
A high‐order discrete‐time IIR low‐pass with complex poles using charge sampling is presented in a single‐stage structure by using a mathematical strategy. In comparison with the analog complex‐poles Gm‐C filters, the proposed filter consumes lower power and has good linearity, and all of the tunings are implemented only by capacitor sizes. The proposed filter is a seventh‐order Butterworth, but this method can be generalized to implement other complex pole filters like Tchebyshev and Elliptic. Post‐layout simulation results in 130‐nm complementary metal‐oxide‐semiconductor (CMOS) show an IIP3 of +18 dBm and a noise figure of 5 dB. The filter has a rejection of more than 110 dB in its stop band and consumes 1.5 mW with a 1.6‐V supply voltage, and circuit occupies an about 0.12 mm2 of silicon.
This paper presents, a novel digital foreground calibration technique in order to reduce the effects of timing-skew in time-interleaved analog-to-digital converters (ADCs). The proposed technique implementation is simple and helps to achieve very low power consumption. This technique is based on the using of a simple reference comparator which is synchronized by one of sub-channels in each cycle of calibration. Also the detection and correction are implemented by a simple LMS loop that guarantee the convergence of algorithm. Finally, simulation results show that the new approach method can effectively correct timing errors for a specified input signal, and achieves a low power consumption, low computational complexity and high convergence speed and also verify theoretical equations for it.
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