SUMMARYThis article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxidesemiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18 μm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on-chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.

Abstract-A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 µm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF.

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Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process.

This paper presents an output-capacitorless class-AB low-dropout (LDO) regulator with load current sinking and sourcing ability. The proposed LDO consists of two complementary pass transistors, controlled using a level shifter technique. The transient improvement section applied to the gates of the pass devices enhances the transient performance of the LDO. The proposed LDO is designed in TSMC 0.18 μm CMOS process with input and output voltages of 1.2-2.5 V and 1 V, respectively, 10 pF output capacitor, and quiescent current of 3.14 μA, and is capable to sink and source maximum load currents of ±100 mA, giving the current efficiency of 99.99%.

A new design based on the flipped-structure for RF active inductors is presented. The conventional flipped-active inductor (FAI) composed of only two transistors is considered as a starting structure. However, it suffers from low-voltage swing, which increases the nonlinearity. Additionally, it requires high power consumption to achieve adequate inductance and quality factor values. A circuit topology named cascoded FAI (CASFAI) based on the basic FAI is proposed. A common-gate transistor added in the feedback path of the proposed CASFAI results in an increase of the voltage swing and linearity as well as the feedback gain. The performance metrics of such active inductors are benchmarked by analytical models and validated in the ADS using a 0.18 µm CMOS process. The results indicate that the CASFAI can achieve a notably higher quality factor and higher inductance values while consuming less power in comparison to the basic FAI.Postprint (published version

In this paper, a CMOS wide-band second-order voltage-mode allpass filter as a time delay cell is proposed. The proposed all-pass filter is made up of solely two transistors as active elements and four passive components. This filter demonstrates a group delay of approximately 60 ps within a bandwidth of 5 GHz, achieving maximum delay-bandwidth-product (DBW). The proposed circuit is highly linear and has an input-referred 1-dB compression point P 1dB of 2 dBm. The power consumption of the proposed circuit is only 10.3 mW. On the other hand, an active inductor is employed in the all-pass filter instead of a passive RLC tank, thereby the three passive components are eliminated, in order to tune the time delay and improve the size. In this case, even though the power consumption increases, the time delay can be controlled across an improved bandwidth of approximately 10 GHz. Moreover, the circuit demonstrates a 1-dB compression point P 1dB of 18 dBm. The proposed all-pass filter is simulated in TSMC 180-nm CMOS process parameters.

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