This paper evaluates the performance of the Neural Architecture Search Network (NASNet) in the automatic detection of COVID-19 (Coronavirus Disease 2019) from chest x-ray images. COVID-19 is a disease caused by Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-CoV-2) that produces in patients fever, cough, shortness of breath, muscle pain, sputum production, diarrhea, and even sore throat. The virus spreads through the air, and to date, is expanding as a global pandemic. There is no vaccine, and it is fatal to approximately 2-7% of the infected population. Among the clinical and paraclinical characteristics of infected patients, nodules have been identified in images of chest x-rays that can be visually identified, producing a simple, rapid, and generally available method of identification. However, the rapid spread of the disease means that there is a lack of specialized medical personnel capable of identifying it, which is why automated schemes are being developed. We propose the tuning of a NASNet-type convolutional model to automatically determine the initial state of a patient in the triage process or intervention protocol of health care centers. The neural network is trained with public images of cases positively identified as patients infected with the virus and patients in normal conditions without infection. Performance evaluation is also done with real images unknown to the neuronal model. As for performance metrics, we use the function of loss of cross-entropy (categorical cross-entropy), the accuracy (or success rate), and the MSE (Mean Squared Error). The tuned model was able to correctly classify the test images with an accuracy of 97%.
Abstract-This paper shows the modeling of a linear-assisted or hybrid (linear & switching) DC-DC converters. In this kind of converters, an auxiliary linear regulator is used, which objective is to cancel the ripple at the output voltage and provide fast responses for load variations. On the other hand, a switching converter, connected in parallel with the linear regulator, allows to supply almost the whole output current demanded by the load. The objective of this topology is to take advantage of the suitable regulation characteristics that series linear voltage regulators have, but almost achieving the high efficiency that switching DC-DC converters provide. Linear-assisted DC-DC converters are feedback systems with potential instability. Therefore, their modeling is mandatory in order to obtain design guidelines and assure stability of the implemented power supply system.
SUMMARYThis article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxidesemiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18 μm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on-chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.
Abstract-A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 µm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.