We propose carbon as new resistive memory material for non-volatile memories and compare three allotropes of carbon, namely carbon nanotubes, graphene-like conductive carbon and insulating carbon for their possible application as resistance-change material in high density non-volatile memories. Repetitive high-speed switching and the potential for multi-level programming have been successfully demonstrated.
This paper presents the resufb on the patterning of shalfow french isolation for the 70nm DRAM technology node on 300mm wafers. Using a new friple hard mask approach incorporating a carbon plm patterns with 70nm CD and STI depth of abaut 250nm could be achieved.
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A practical approach, adopting a clever litho trim, to spacer double patterning is investigated in detail. In order to produce quarterpitch small lines of dense arrays ͑with pitch fragmentation techniques͒, state-of-the-art ArF photoresists can be used with a subsequent trim etch, to get the tiny line widths on desired target. Critical dimension ͑CD͒ control during the trim etch process plays a crucial role. Therefore, we investigated the application of a litho trim in order to reduce the trim etch close to zero bias. This approach has the further advantage to allow the printing of small spaces together with small lines, which reduces the k 1 and, therefore, the theoretical resolution. Applying CD trim by litho "overexposure," thin ArF bilayer system ͑silicon containing resist on spin-on carbon underlayer͒ showed basic suitability at k 1 = 0.146 at half pitch of 3xnm with a sufficient process window and a good CD uniformity after litho and after etch. ArF single-layer resists suffer from pattern collapse and resist thickness loss at defocus. For spacer deposition directly on resist, the control of profiles and film thicknesses is shown to be difficult using single-layer resists and more likely to be achieved with bilayer resists. It is also shown that spacer-based double patterning can generate good CD uniformity by use of bilayer resist and litho trim, both with an a-Si carrier and bilayer resist carrier ͑underlayer͒.
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