A series electrostatic discharge (ESD) diode structure is proposed to minimise the degradation induced by thermal interaction between series connected diodes. The proposed series diode is constructed using a distributed cell-based ESD diode. To verify the feasibility of the proposed structure, single and series diodes are designed using the typical and the proposed structures. From the experimental results, it is proved that the ESD survival levels of the proposed series diode are nearly identical to those of the single diode, unlike the case of typical series diodes.
In this study, we design a differential CMOS power amplifier using a 180-nm SOI RFCMOS process for 802.11n (64-QAM, 20 MHz bandwidth, 9.6 dB peak to average power ratio (PAPR)) applications. To minimize the chip area and mismatch in differential signals, we propose a layout method with an inter-stage matching network using a split inductor. By virtue of the symmetrical layout of the proposed split inductor, the mismatch in the differential signals is minimized, while the interconnection lines between the driver and power stages are shortened to minimize the overall chip area and the loss induced by the resistive parasitic components. The designed power amplifier is measured using a wireless local area network (WLAN) 802.11n signal to verify the feasibility of the proposed layout technique. The power amplifier achieved 20.34 dBm output power, while the measured EVM for the 802.11n applications is satisfied. From the measured results, we successfully prove the feasibility of the proposed power amplifier.
In this work, we propose a balun embedded driver stage to enhance the bandwidth and minimize the chip size of a differential CMOS power amplifier. By removing the passive input transformer, the bandwidth and chip size are improved. The proposed driver stage acts as an input balun as well as the driver stage for the power stage. The proposed driver is composed of a cascade connected PMOS, an inductor, and NMOS to generate the differential output signal. For the function of the input balun, the gate of the PMOS is connected to the drain of the NMOS. To verify the feasibility of the proposed balun embedded driver stage, we design a differential CMOS power amplifier for 5-GHz IEEE 802.11n WLAN applications. The designed power amplifier is fabricated using the 180-nm SOI RF CMOS process. The measured 3-dB bandwidth is approximately 2.5 GHz. The chip size of the fully integrated power amplifier, including input and output matching networks and test pads, is 0.885 mm 2. The measured maximum output power is 20.18 dBm with a PAE of 10.16%.
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