Electrostatic discharge protection devices with series connection using distributed cell‐based diodes

Son, Minoh; Park, Changkun

doi:10.1049/el.2013.3753

Cited by 7 publications

(2 citation statements)

References 4 publications

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“…In order to reduce the parasitic capacitance or provide the large signal-swing tolerance, the ESD protection diodes in stacked configuration have been presented [36,37], as shown in Figure 12(a). The device cross-sectional views of the conventional stacked diodes are shown in Figure 12(b) and (c).…”

Section: Esd Protection Circuit Design: Type IImentioning

confidence: 99%

Low-C ESD Protection Design in CMOS Technology

Lin¹

2019

Electrostatic Discharge - From Electrical Breakdown in Micro-Gaps to Nano-Generators

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Electrostatic discharge (ESD) protection design is needed for integrated circuits in CMOS technology. The choice for ESD protection devices in the CMOS technology includes diode, MOSFET, and silicon controlled rectifier (SCR). These ESD protection devices cause signal losses at high-frequency input/output (I/O) pads due to the parasitic capacitance. To minimize the impacts from ESD protection circuit on high-frequency performances, ESD protection circuit at I/O pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for high-frequency applications in CMOS technology is presented in this chapter. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with high-frequency circuits. As the operating frequencies of high-frequency circuits increase, on-chip ESD protection designs for high-frequency applications will continuously be an important design task.

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Section: Esd Protection Circuit Design: Type IImentioning

confidence: 99%

Low-C ESD Protection Design in CMOS Technology

Lin¹

2019

Electrostatic Discharge - From Electrical Breakdown in Micro-Gaps to Nano-Generators

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“…ESD protection in high-speed ICs becomes more challenging than others because it requests low parasitic capacitance, low leakage current and almost zero series resistance [8,9,10]. To address this, dual-diode based ESD protection circuits, often named "rail-based" ESD protection circuits [11], are widely implemented for radio-frequency (RF), digital and high-speed interface ICs [12,13,14,15,16,17,18,19,20,21]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Lai

Wang

et al. 2019

IEICE Electron. Express

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In this paper, ESD triggering mechanism of the parasitic PNP bipolar transistor in rail-based ESD protection circuits was investigated. The device simulation results show that the triggering voltage of the parasitic PNP varies with the geometry of the base region (e.g., the spacing between P+ and N-well). Furthermore, the test structures of parasitic PNP devices with different width of collector and base region were fabricated using the 65 nm low-k logic/Mixed-Mode CMOS process and characterized with the transmission line pulse (TLP) system. Both simulation and experimental results demonstrated that the triggering voltage of parasitic PNP structures has strong dependence on the base region and the simulation results also show that the triggering voltage is significantly affected by the spacing between P-well and N-well.

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