No abstract

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 µVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-µm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems. Index Terms-Multi-channel neural recording system, biomedical application, high power efficiency, power and area trade-off, dual S/H, low-noise neural amplifier, current reuse, NEF, SAR ADC, capacitor-less LDO I. INTRODUCTION imultaneous recording of neuropotentials from the brain over a large number of electrodes provides an effective Manuscript received September 28, 2012.

An integrated CMOS ultrawideband wireless telemetry transceiver for wearable and implantable medical sensor applications is reported in this letter. This high duty cycled, noncoherent transceiver supports scalable data rate up to 10 Mb/s with energy efficiency of 0.35 nJ/bit and 6.2 nJ/bit for transmitter and receiver, respectively. A prototype wireless capsule endoscopy using the proposed transceiver demonstrated in vivo image transmission of 640 × 480 resolution at a frame rate of 2.5 frames/s with 10 Mb/s data rate.

A highly efficient rectifier for wireless power transfer in biomedical implant applications is implemented using 0.18-μm CMOS technology. The proposed rectifier with active nMOS and pMOS diodes employs a four-input common-gate-type capacitively cross-coupled latched comparator to control the reverse leakage current in order to maximize the power conversion efficiency (PCE) of the rectifier. The designed rectifier achieves a maximum measured PCE of 81.9% at 13.56 MHz under conditions of a low 1.5-V pp RF input signal with a 1-kΩ output load resistance and occupies 0.009 mm 2 of core die area.

Individuals with tetraplegia lack independent mobility, making them highly dependent on others to move from one place to another. Here, we describe how two macaques were able to use a wireless integrated system to control a robotic platform, over which they were sitting, to achieve independent mobility using the neuronal activity in their motor cortices. The activity of populations of single neurons was recorded using multiple electrode arrays implanted in the arm region of primary motor cortex, and decoded to achieve brain control of the platform. We found that free-running brain control of the platform (which was not equipped with any machine intelligence) was fast and accurate, resembling the performance achieved using joystick control. The decoding algorithms can be trained in the absence of joystick movements, as would be required for use by tetraplegic individuals, demonstrating that the non-human primate model is a good pre-clinical model for developing such a cortically-controlled movement prosthetic. Interestingly, we found that the response properties of some neurons differed greatly depending on the mode of control (joystick or brain control), suggesting different roles for these neurons in encoding movement intention and movement execution. These results demonstrate that independent mobility can be achieved without first training on prescribed motor movements, opening the door for the implementation of this technology in persons with tetraplegia.

This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a Content-Addressable-Memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 µs. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V ~ 0.6 V by the proposed CAM-assisted circuit. Index Terms-Bitline leakage equalization, content addressable memory, energy efficiency improvement, ultra-low voltage SRAM design I. INTRODUCTION TATE-OF-THE-ART DSP cores and advanced healthcare SoCs [1],[2] benefit from availability of on-chip SRAMs with substantially reduced power dissipation and improved energy efficiency. Integrated SRAMs play a crucial role in providing the required density, performance, power, and energy Manuscript

In this paper, an integrated electrocardiogram (ECG) signal-processing scheme is proposed. Using a systematic wavelet transform algorithm, this signal-processing scheme can realize multiple functions in real time, including baseline-drift removal, noise suppression, QRS detection, heart beat rate prediction and classification, and clean ECG reconstruction. Utilizing the novel low-cost hardware architecture, the proposed ECG signal-processing scheme is implemented in application-specific integrated circuits with 0.18 μ m CMOS technology. This ECG signal-processor chip achieves low area and power consumptions, and is highly suitable for wearable applications of long-term cardiac monitoring.

Monitoring blood flow rate inside prosthetic vascular grafts enables an early detection of the graft degradation, followed by the timely intervention and prevention of the graft failure. This paper presents an inductively powered implantable blood flow sensor microsystem with bidirectional telemetry. The microsystem integrates silicon nanowire (SiNW) sensors with tunable piezoresistivity, an ultralow-power application-specific integrated circuit (ASIC), and two miniature coils that are coupled with a larger coil in an external monitoring unit to form a passive wireless link. Operating at 13.56-MHz carrier frequency, the implantable microsystem receives power and command from the external unit and backscatters digitized sensor readout through the coupling coils. The ASIC fabricated in 0.18-μm CMOS process occupies an active area of 1.5 × 1.78 mm (2) and consumes 21.6 μW only. The sensors based on the SiNW and diaphragm structure provide a gauge factor higher than 300 when a small negative tuning voltage (-0.5-0 V) is applied. The measured performance of the pressure sensor and ASIC has demonstrated 0.176 mmHg/√Hz sensing resolution.