hole-injection, respectively. Good punch through immunity and low operation current are achieved because the lateral A new method to program and erase NAND devices electrical field is eliminated. The bias conditions for the without using high voltage Fowler-Nordheim (FN) stressing memory operation are summarized in Table 2. is investigated. Impact Ionization generated substrate Hot Fig. 2 shows the simulated results using ISE-TCAD for Electron (JIBE) and Band to Band tunneling Hot Hole a device with gate length of 0.Im. For erase operation, the (BBHH) are proposed for SONOS-type NAND flash memory electrical filed is concentrated at the overlap region between application. Both junctions are biased with the same voltage gate/junctions and hot-holes are generated through BBHH to perform double-side-charge-injection without lateral mechanism. For program operation, the electrical field is electrical field induced current. A novel divided bit line concentrated at the bottom of junctions and hot-electron is architecture is introduced to achieve this operation. Fast generated by impact ionization of hot-hole through a program and erase speed of < 100s is achieved. Good 10K Junction-BBHH mechanism. These simulation results cycling endurance and high temperature data retention are indicate that the mechanism for hot-electron programming demonstrated. IIHE/BBHH for floating gate memory and and hot-hole erasing are different. body-tied FinFET-type SONOS are also demonstrated.Device Characterization Introduction Fig. 3 and Fig. 4 show the IIBE-program and BBHHNitride trapping memory has simple fabrication process, erase curves at various Vd/Vs voltages. The efficiency of the as well as no floating gate coupling and cross talk issues and proposed memory operation can be controlled by the junction is thus an ideal candidate for further scaling of NAND flash voltage. An operation window >8V (PV>6V and EV<-2V) is [1]. However, electrons are captured in deep traps and achieved, promising for MLC applications. The I-V erasing by -FN is very slow. Recently, barrier engineering characteristics of different memory states are shown in Fig. 5. (BE-SONOS) to allow fast -FN substrate hole erasure is The parallel shift of I-V curves indicates that for a short proposed as a promising solution [2]. channel device the local injection of charges from both In this work, we propose a new programming and source and drain is similar to FN induced uniform channel erasing method that does not require high voltage FN injection. operation. By applying the same voltage on the source/drain Fig. 6 shows the efficiency of BBHH-erase as a function junctions simultaneously we can generate efficient impact of gate length Lg. For longer Lg cells, the Vt shift is small ionization hot electrons (IIHE) for very high speed after erase operation because the channel center is not erased. programming. In addition, a novel Bit-by-Bit Correction Thus only short channel devices with Lg <0.16tm are (BBC) method is proposed to repair erratic bits and to tighten efficien...
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