An Asymmetric Two-Side Program With One-Side Read (ATPOR) Device for MultiBit Per Cell MLC Nitride-Trapping Flash Memories

Design of Unique Four-Bit/Cell Polycrystalline Silicon–Oxide–Silicon Nitride–Oxide–Silicon Devices Utilizing Vertical Channel of Silicon Pillar

“…Because the tail distribution can affect the read operation of the other side in conventional NROM devices, the spatial distribution of the trapped charges and their transient behavior in the nitride layer are important for enhancing the reliability of the 2-bit/cell operation as cell size decreases. 15,16) Therefore, a separation of the twin-bit nitrides suppresses the lateral charge diffusion of trapped charges, resulting in the minimization of the degradation and the spread of the trapped charges. 17,18) The proposed SPVC-SONOS cells require enhancement mode threshold voltages (V th ) for both the erase and the program states to ensure that unselected cells do not contribute sense current to the selected bit line.…”

Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

“…As an alternative, NVM devices with multi-bit operation have received a great interest to increase the bit-density without compromising area [4][5][6][7]. For this purpose, non-conductive materials such as silicon nitride, high-k dielectrics and nanocrystals are used instead of the conventional poly-Si to localize the injected charges [8][9][10][11][12][13][14].…”