A novel approach for fast generation of video holograms of three-dimensional (3-D) moving objects using a motion compensation-based novel-look-up-table (MC-N-LUT) method is proposed. Motion compensation has been widely employed in compression of conventional 2-D video data because of its ability to exploit high temporal correlation between successive video frames. Here, this concept of motion-compensation is firstly applied to the N-LUT based on its inherent property of shift-invariance. That is, motion vectors of 3-D moving objects are extracted between the two consecutive video frames, and with them motions of the 3-D objects at each frame are compensated. Then, through this process, 3-D object data to be calculated for its video holograms are massively reduced, which results in a dramatic increase of the computational speed of the proposed method. Experimental results with three kinds of 3-D video scenarios reveal that the average number of calculated object points and the average calculation time for one object point of the proposed method, have found to be reduced down to 86.95%, 86.53% and 34.99%, 32.30%, respectively compared to those of the conventional N-LUT and temporal redundancy-based N-LUT (TR-N-LUT) methods.
In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy consumption of a conventional and the proposed neuron circuits. In a single neuron circuit with microsecond duration pulses, 58% of the energy consumption is reduced by incorporating a FBFET. We performed SPICE compact modeling of FBFET, and its parameters were fitted to match the measurement results of the fabricated FBFET. Then, we conducted a circuit simulation to verify the operating neural networks. We implemented a single layer spiking neural network (SNN) that had resistive synaptic devices. In the SNN simulation, approximately 94% of the average power consumption of all output neurons was reduced.
The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This
paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate
the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized
in upcoming high-performance hardware SNN systems.
We have developed a capacitor-less I&F neuron circuit with a dual gate positive feedback fieldeffect transistor (FBFET) and successfully co-integrated FBFET and CMOS in a wafer. By implementing the neuron circuit with FBFET, we can overcome the limits of conventional CMOS, reduce energy consumption, and imitate the biological neuron. The floating body of the FBFET can replace the membrane capacitor that occupies a large area and performs leaky integration of the neuron. Due to the extremely low sub-threshold swing of the FBFET (less than 0.528mv/dc), energy consumption of the neuron is significantly reduced by suppressing sub-threshold current. Finally, we analyzed the fabricated neuron circuit operation, retention time of the integrated charges and energy consumption compare to conventional CMOS neuron circuit.INDEX TERMS Integrate-and-fire neuron circuit, positive feedback FET, low energy consumption, floating body effect.
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