Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

Abstract

In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy consumption of a conventional and the proposed neuron circuits. In a single neuron circuit with microsecond duration pulses, 58% of the energy consumption is reduced by incorporating a FBFET. We performed SPICE compact modeling of FBFET, and its parameters were fitted to match the measurement results of the fabricated FBFET. Then, we conducted a circuit simulation to verify the operating neural networks. We implemented a single layer spiking neural network (SNN) that had resistive synaptic devices. In the SNN simulation, approximately 94% of the average power consumption of all output neurons was reduced.

A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback FET Co-Integrated With CMOS

“…In our previous work, we analyzed operation mechanism and electrical characteristics of the FBFET [23]. In this fabrication, we improved sub-threshold slop (SS) and on/off current ratio by reducing gate length, rapid thermal annealing time and increasing annealing temperature.…”

“…But these devices have low endurance, stochastic switching problems for use in neuron circuits and most of the materials that construct the device are not compatible with CMOS process. In previous works, we have analyzed the energy consumption caused by the I SC in conventional neuron circuit and developed low-energy neuron circuit with positive feedback FET (FBFET) that perfectly suppressed the I SC and investigated operation mechanism and electrical characteristics of the FBFET by TCAD and SPICE simulation work [23]. But, in previous works the neuron circuit used membrane capacitor to integrate input signals.…”

Integrate-and-Fire Neuron Circuit Without External Bias Voltages

“…In Table 1 , the CMOS, floating-gate FET and FBFET neuron circuits reported by other research groups require 5–23 elements with capacitors, and more than 1–10 external bias lines which require extra peripheral circuit for generating bias voltages, causing these neuron circuits to consume high power and energy ( Indiveri et al, 2006 ; Kornijcuk et al, 2016 ; Choi et al, 2018 ; Kwon et al, 2018 ; Kim et al, 2019 ; Wang and Khan, 2019 ; Zhang and Wijekoon, 2019 ; Chavan et al, 2020 ; Woo et al, 2020 ). The FBFET neuron circuit has relatively low energy consumption compared to others except ours, but this neuron circuit requires extra peripheral circuits for generating voltage bias and controllers for the I&F operation ( Choi et al, 2018 ; Kwon et al, 2018 ; Woo et al, 2020 ). The PDSOI MOS-based neuron circuit also requires an external reset circuit applied with changeable gate voltage to reset the membrane potential ( Chavan et al, 2020 ).…”

“…Despite their advantages over Von-Neumann computing architectures in terms of energy efficiency, neuron circuits, driven by spiking neural networks (SNNs), still need more power for their integrate-and-fire (I&F) operations than biological neurons ( Choi et al, 2018 ). For most neuron circuits, particularly those using complementary metal-oxide semiconductor (CMOS), feedback field-effect-transistor (FBFET), and floating gate FET (FGFET) ( Indiveri et al, 2006 ; Kornijcuk et al, 2016 ; Choi et al, 2018 ; Kwon et al, 2018 ; Kim et al, 2019 ; Wang and Khan, 2019 ; Zhang and Wijekoon, 2019 ; Chavan et al, 2020 ; Woo et al, 2020 ), the presence of numerous transistors and external bias lines result in relatively high power consumption for the I&F operations. Thus, for energy-efficient neuron circuits, suppression in numbers of transistors, absence of external bias lines, and use of steep switching devices with extremely low subthreshold swings ( SS s) are needed ( Abbott, 1999 ; Izhikevich, 2003 ; Cheung, 2010 ); the steep switching devices are crucially necessary for a substantial reduction in power consumption of neuron circuits.…”

Photonic Synapses for Ultrahigh‐Speed Neuromorphic Computing

“…Learning and memory can be implemented by regulating the weight of synapses linking two adjacent neurons. Various electronic synapses and neurons have been developed by different technologies such as complementary metal‐oxide‐semiconductor integrated circuits, transistors, and memristors . Furthermore, the corresponding neuromorphic circuits have been constructed, in which simple cognitive functions such as pattern classification and sparse coding can be realized .…”