A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products. IntroductionAs CMOS technology scales down to 22nm, traditional planar transistor architectures [1-3] have reached a fundamental limit for the required short channel control necessary to continue scaling at the rate dictated by Moore's Law. Recently, novel 3-D Tri-Gate transistors have been proven to be capable of high volume manufacturing for high performance CPU products [4]. This paper reports, for the first time, a leading edge 22nm SoC process technology featuring 3-D Tri-Gate transistors which employs high speed logic transistors, low standby power transistors and highvoltage tolerant transistors simultaneously in a single SoC chip to support a wide range of products, including premium smart phones, tablets, netbooks, embedded systems, wireless communications, and ASIC products.

Nanoelectromechanical (NEM) switches have received widespread attention as promising candidates in the drive to surmount the physical limitations currently faced by complementary metal oxide semiconductor technology. The NEM switch has demonstrated superior characteristics including quasi-zero leakage behaviour, excellent density capability and operation in harsh environments. However, an unacceptably high operating voltage (4-20 V) has posed a major obstacle in the practical use of the NEM switch in low-power integrated circuits. To utilize the NEM switch widely as a core device component in ultralow power applications, the operation voltage needs to be reduced to 1 V or below. However, sub-1 V actuation has not yet been demonstrated because of fabrication difficulties and irreversible switching failure caused by surface adhesion. Here, we report the sub-1 V operation of a NEM switch through the introduction of a novel pipe clip device structure and an effective air gap fabrication technique. This achievement is primarily attributed to the incorporation of a 4-nm-thick air gap, which is the smallest reported so far for a NEM switch generated using a 'top-down' approach. Our structure and process can potentially be utilized in various nanogap-related applications, including NEM switch-based ultralow-power integrated circuits, NEM resonators, nanogap electrodes for scientific research and sensors.

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A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.

A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.

Electronics that degrade after stable operation for a desired operating time, called transient electronics, are of great interest in many fields, including biomedical implants, secure memory devices, and environmental sensors. Thus, the development of transient materials is critical for the advancement of transient electronics and their applications. However, previous reports have mostly relied on achieving transience in aqueous solutions, where the transience time is largely predetermined based on the materials initially selected at the beginning of the fabrication. Therefore, accurate control of the transience time is difficult, thereby limiting their application. In this work, we demonstrate transient electronics based on a water-soluble poly(vinyl alcohol) (PVA) substrate on which carbon nanotube (CNT)-based field-effect transistors were fabricated. We regulated the structural parameters of the PVA substrate using a three-dimensional (3D) printer to accurately control and program the transience time of the PVA substrate in water. The 3D printing technology can produce complex objects directly, thus enabling the efficient fabrication of a transient substrate with a prescribed and controlled transience time. In addition, the 3D printer was used to develop a facile method for the selective and partial destruction of electronics.

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