A 32nm SoC platform technology with 2&lt;sup&gt;nd&lt;/sup&gt; generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

Jan, C.-H.; Agostinelli, M.; Buehler, Markus J.; Chen, Z.-P.; Choi, S.-J.; Curello, G.; Deshpande, H.; Gannavaram, S.; Hafez, W.; Jalan, U.; Kang, Min-Ho; Kolar, Pramod; Komeyli, K.; Landau, Barbara; Lake, Adam; Lazo, N.; Lee, S.-H.; Leo, Tulus; Jiang, Lin; Lindert, N.; Ma, Siying; McGill, Lisa; Meining, C. J.; Paliwal, Ayushi; Park, J.; Phoa, K.; Post, Ian; Pradhan, N.; Prince, M.; Rahman, Anisur; Rizk, J.; Rockford, L.; Sacks, G.; Schmitz, A.; Tashiro, Hiroyuki; Tsai, C.; Vandervoorn, P.; Xu, Jian; Yang, L.; Yeh, J.-Y.; Yip, J.; Zhang, K.; Zhang, Y.; Bai, P.

doi:10.1109/iedm.2009.5424258

Cited by 51 publications

(29 citation statements)

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“…Then the rest of the process flow proceeds in similar steps as for the planar devices such as well doping, dummy gate deposition and patterning, spacer deposition and etching, epitaxial source/drain (S/D) formation, inter layer dielectric zero(ILD0) and chemical mechanical polish (CMP), dummy gate removal, high-k and metal-gate (HKMG) formation, self-aligned contact (SAC) formation, local interconnects (LI), and finally back-end-of-line (BEOL) interconnect construction [21,22].…”

Section: Process Integration Of New Transistor Architecturementioning

confidence: 99%

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The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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Section: Process Integration Of New Transistor Architecturementioning

confidence: 99%

“…Fin etching in bulk silicon has to be controlled by a timer Figure 2 [21][22][23][24]. These challenges relate to issues: precise and uniform fin formation, 3D gate and spacer patterning, uniform junction formation in fin, and severer layout dependent effect (LDE) on stress.…”

Section: Precise and Uniform Fin Formationmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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“…Planar spiral inductors are common and Intel corp. has demonstrated inductors with quality factors (Q's) greater than 20, utilizing 8 µm of highly conductive metal. 39 Surface mount wire wound inductors are more complex to fabricate and they require mounting. However, they provide unrivaled performance, with inductance values greater than 10 nH and quality factors greater than 50.…”

Section: Inkjet-printed Rf Inductorsmentioning

confidence: 99%

Robust Design of a Particle-Free Silver-Organo-Complex Ink with High Conductivity and Inkjet Stability for Flexible Electronics

Vaseem

McKerricher

Shamim

2015

ACS Appl. Mater. Interfaces

101

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Currently, silver nanoparticle based inkjet ink is commercially available. This type of ink has several serious problems such as a complex synthesis protocol, high cost, high sintering temperatures (~200 0 C), particle aggregation, nozzle clogging, poor shelf life, and jetting instability. For the emerging field of printed electronics, these short comings in conductive inks are barriers for their wide spread use in practical applications. Formulating particle free silver inks has potential to solve these issues, and requires careful design of the silver complexation.The ink complex must meet various requirements, such as in-situ reduction, optimum viscosity, 2 storage and jetting stability, smooth uniform sintered films, excellent adhesion, and high conductivity. This study presents a robust formulation of silver-organo-complex (SOC) ink, where complexing molecules act as reducing agents. The 17 weight percent silver loaded ink was printed and sintered on a wide range of substrates with uniform surface morphology and excellent adhesion. The jetting stability was monitored for 5 months to confirm that the ink was robust and highly stable with consistent jetting performance. Radio frequency inductors which are highly sensitive to metal quality were demonstrated as a proof of concept on flexible PEN substrate. This is a major step towards producing high quality electronic components with a robust inkjet printing process.

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“…For a given technology node, devices with low normally show larger but also much larger when compared to high-devices [5], [12]. Low-devices with larger are used in the critical paths to reduce delay and meet timing constraints.…”

Section: A Conventional Multi-threshold-voltage Technologymentioning

confidence: 99%

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Zhang

Tang

Gaillardon

et al. 2014

IEEE Trans. Circuits Syst. I

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Abstract-Silicon nanowire transistors with Schottky-barrier contacts exhibit both -type and -type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polarity gate. The device can be configured as -type or -type by controlling the polarity gate voltage. This paper extends this approach by using three independent gates and shows its interest to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions, targeting either high-performance or low-leakage applications. Dual-threshold-voltage design is thereby achievable through the use of a wiring scheme on an uncommitted pattern. With the polarity controllability of the three-independent-gate device, a range of logic functions is also obtained by replacing and GND by complementary input signals. Synthesis results of ISCAS'85 and VTR sequential benchmark circuits with these devices show, before place and route, comparable performance and 51% reduction of leakage power consumption compared to 22-nm low-standby-power FinFET technology.

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A 32nm SoC platform technology with 2<sup>nd</sup> generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

Cited by 51 publications

References 0 publications

The Challenges of Advanced CMOS Process from 2D to 3D

The Challenges of Advanced CMOS Process from 2D to 3D

Robust Design of a Particle-Free Silver-Organo-Complex Ink with High Conductivity and Inkjet Stability for Flexible Electronics

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

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