This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 µm width and 450 nm depth) with a density of 1.09 × 10 5 cm −2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C-V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing D IT levels of 3.3 × 10 11 cm −2 eV −1 at E C −E T = 0.2 eV. The homo-epitaxially grown 3C-SiC material's suitability for MOS applications could also be confirmed by leakage current measurements.

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The cubic polytype (3C-) of Silicon Carbide (SiC) is an emerging semiconductor technology for power devices. The featured isotropic material properties along with the Wide Band Gap (WBG) characteristics make it an excellent choice for power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). It can be grown on Silicon (Si) substrates which is itself advantageous. However, the allowable annealing temperature is limited by the melting temperature of Si. Hence devices making use of 3C-SiC on Si substrate technology suffer from poor or even almost negligible activation of the p-type dopants after ion implantation due to the relatively low allowable annealing temperature. In this paper, a novel process flow for a vertical 3C-SiC-on-Si MOSFET is presented to overcome the difficulties that currently exist in obtaining a pbody region through implantation. The proposed design has been accurately simulated with Technology Computer Aided Design (TCAD) process and device software. To ensure reliable prediction, a previously validated set of material models have been used. Further, a channel mobility physics model was developed and validated against experimental data. The output characteristics of the proposed device demonstrated promising performance, what is potentially the solution needed and a huge step towards the realisation of 3C-SiC-on-Si MOSFETs with commercially grated characteristics.

A low p-n built-in potential (1.75 V) makes 3C-SiC an attractive choice for medium voltage bipolar or charge balanced devices. Until recently, most 3C-SiC had been grown on Si, and power device fabrication had therefore been hindered by issues such as high defect density and limited processing temperature, while devices were necessarily limited to lateral structures. In this work, we present the fabrication and characterisation of a vertical PiN diode using bulk 3C-SiC material. A p-type ohmic contact was obtained on Al implanted regions with a specific contact resistance ~10 -3 Ω.cm 2 . The fabricated PiN diode has a low forward voltage drop of 2.7 V at 1000 A/cm 2 , and the on-off ratio at ±3 V is as high as 10 9 . An ideality factor of 1.83-1.99 was achieved, and a blocking voltage of ~110 V was observed using a singlezone junction termination design.

Cubic (3C-) silicon carbide (SiC) metal oxide semiconductor (MOS) devices have the potential to achieve superior performance and reliability. The effective channel mobility can be significantly higher compared to other SiC polytypes due to the smaller concentration of active SiC/SiO2 interface traps and the gate leakage current can be smaller than other SiC polytypes and silicon (Si) because of the more favourable conduction band offset between 3C-SiC and silicon dioxide (SiO2). This work examines the 3C-SiC/SiO2 n-MOS interface and makes use of three independent sets of experimental data to derive and validate a comprehensive model of the inversion layer mobility in 3C-SiC n-MOS structures. The model derived in this work can be used by technology computer aided design (TCAD) tools and can predict the channel mobility with reasonable accuracy for gate voltages ranging 0V -20V, and for temperatures ranging 300K -473K. The ability to reproduce correctly the physical phenomena affecting the 3C-SiC/SiO2 n-MOS channel mobility in TCAD through an appropriately parameterised model is imperative for the design and optimization of MOS devices like MOSFETs and IGBTs and the further development of 3C-SiC device technology.