In BGA package assembly, the solder ball attach process is one of the yield off points that impacts the overall product yield and cycle time because of the need to rework. From the beginning of BGA product manufacturing the race to achieve high solder ball attach yields has spurned various ball attach technology from flux printing to flux pin transfer, a multitude of flux formulations by various flux suppliers, improvement in solder ball pad finishes by substrate suppliers, and many other process improvement iteration. Today, the most popular ball attach technology in the industry is the use of pin transfer using tacky flux on solder on BGA pad (SOPBGA), Imm Sn, CuOSP, and ENIG. Yet, the solder ball attach process continues to suffer missing balls, joined balls, and bridging balls, impacting the overall cycle time due to rework. This study shows the use of dippable paste, a novel ball attach material replacing flux that's compatible with pin transfer equipment technology and which pushes the first pass yield to 100%, virtually eliminating rework and could potentially reduce manufacturing cycle time.Dippable paste has been used mostly in package-onpackage technology but most formulations are no-clean. A new water-soluble formulation was successfully prepared and applied to normal pin transfer ball attach process for the first time. The solder powder in the dippable paste improved wettability onto the pad finish. Results showed 100% first pass yield on FCBGA samples with SOPBGA, Imm Sn, ENIG, and CuOSP pad finishes. It also showed comparable coplanarity, solder ball height, solder ball diameter, solder ball shear, solder ball pull, and x-y pitch values with flux process. The robustness of the process is confirmed with perfect first pass yield even on poor surface conditions.
Flip Chip (FC) technology has now become the mainstream solution for high performance packages. From commercial gaming machines to high reliability servers, the FC package is gaining more market share over traditional packaging technologies, such as wire bond. Extensive research has been carried out to make the flip chip more robust, smaller foot prints, and excellent performance. FC packages are fabricated typically in two main configurations. Bare die FC packages leave the non active side of the die exposed. This allows the customer to apply their preferred heat dissipation scheme during board level attach. Lidded FC packages use a metallic lid attached to the die. Bare die package can be further subdivided into bare die underfilled package and bare die flip chip molded ball grid array (FCmBGA) package. Each of these packaging configurations has advantages as well as disadvantages. FCmBGA uses molding compound or EMC instead of capillary underfill, to protect FC die, and eliminate the need for a lid. Package warpage reduced a lot by adding a lid with the bare die FC package. However, the package and board level reliability for the above package types are still debatable. In this study test vehicles with three package types with bumps and BGAs are daisy chain to measure in situ data during accelerated tests. Impact of standard vs. low CTE (coefficient of thermal expansion) core substrate, accelerated temperature cycle conditions (temperature cycle condition “B”, “H”, and “J” according to JEDEC), and package level vs. package mounted on the board level reliability will be investigated. Comprehensive reliability data will help to select the right package type for next generation large die large body flip chip application.
Underfill is one of the crucial materials in flip chip (FC) packages. The role of underfill is not only to protect the solder bumps but to minimize package warpage, and to protect the fragile low k dielectric at end of line (EOL), moisture resistance test (MRT), and temperature cycle B (TCB) conditions. As packages move towards green products, the complexity of selecting a good underfill increases. The interaction of high Pb or eutectic solder with the underfill is different than that of Pb free solder. Moreover Pb free solder behavior for FC bumps is just being explored in the literature. Besides Pb free solder, other parameters like die passivation, bump height and pitch, under bump metallurgy (UBM) metallization, and package substrate are also extremely important for underfill selection. As the design of the package continues to change smaller package, tighter bump pitch and thinner core and build up (BU) layers, all of these parameters are directly related to package reliability. Sometimes an underfill good for a smaller die, body size, taller bump height, and pitch doesn’t necessarily mean it will be appropriate for a bigger die with larger body, and tighter bumps. So there are lots of variables in the package that directly affect the reliability. A good underfill should have very good adhesion between underfill and die passivation at room temperature, and moderate adhesion at underfill Tg. Adhesion properties are solely depend on chemistry of the underfill. Therefore to determine a good underfill for a bigger die and body size, we need to have a sequential selection methodology. In this paper a sequential selection methodology is used to eliminate the unsuccessful underfill candidates and select the best one which comfortably satisfies the requirements for all different solder alloys, and a wider range of package geometries. Important selection criteria including underfill workability issues and modeling data are also discussed.
Coreless package substrates are preferred for their superior electrical performance and thin profile compare to conventional substrates with core. However, one of the major concerns with coreless substrate packages is warpage control. It is difficult to meet industry standards for co-planarity because of the high CTE of the coreless substrates and the missing stiff core material in the stack up of the coreless structure. Finite element analysis (FEA) is utilized to investigate the use of coreless substrate in different package configurations. In this study, known stiffening structures such as a stiffener ring, lid and molding options are investigated to characterize the advantages and disadvantages of using each of these structures to control the warpage in an IC package with coreless substrate. Available shadow moiré data is used for initial correlation of the finite element model and further design changes were carried out to stiffen the structure in the final packaged configuration. It is important to understand and make design considerations accordingly to improve assembly yield. Suggestions made depend on the FEA findings which would guide the selection of the stiffening structure for a package with coreless substrate.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.