Tackling the design of a mission-critical system is a rather complex task: different and quite often contrasting dimensions need to be explored and the related trade-offs need to be evaluated. Designing a mass-memory device is one of the typical issues of mission-critical applications: the whole system is expected to accomplish a high level of dependability which highly relies on the dependability provided by the mass-memory device itself. NAND flash-memories could be used for this goal: in fact on the one hand they are nonvolatile, shock-resistant and powereconomic but on the other hand they have several drawbacks (e.g., higher cost and number of erasure cycles bounded). Error Detection And Correction (EDAC) techniques could be exploited to improve dependability of flash-memory devices: in particular binary Bose and Ray-Chaudhuri (BCH) codes are a well known correcting code technique for NAND flash-memories. In spite of the importance of error correction capability several other equally critical dimensions need to be explored during the design of binary BCH codes for a flashmemory based mass-memory device. No systematic approach has so far been proposed to consider them all as a whole: as a consequence a novel design environment with a user-selectable error correction capability is aimed at supporting the design of binary BCH codes for a flash-memory based mass-memory device.
NAND flash memories represent a key storage technology for solid-state storage systems. However, they su↵er from serious reliability and endurance issues that must be mitigated by the use of proper error correction codes. This paper proposes the design and implementation of an optimized Bose-Chaudhuri-Hocquenghem hardware codec core able to adapt its correction capability in a range of predefined values. Code adaptability makes it possible to e ciently trade-o↵, in-field reliability and code complexity. This feature is very important considering that the reliability of a NAND flash memory continuously decreases over time, meaning that the required correction capability is not fixed during the life of the device. Experimental results show that the proposed architecture enables to save resources when the device is in the early stages of its lifecycle, while introducing a limited overhead in terms of area.
Designing a mass-memory device (i.e., a solid-state recorder) is one of the typical issues of mission-critical space system applications. Flash-memories could be used for this goal: a huge number of parameters and trade-offs need to be explored. Flash-memories are nonvolatile, shock-resistant and powereconomic, but in turn have different drawback: e.g., their cost is higher than normal hard disk and the number of erasure cycles is bounded. Moreover space environment presents various issues especially because of radiations: different and quite often contrasting dimensions need to be explored during the design of a flash-memory based solid-state recorder. No systematic approach has so far been proposed to consider them all as a whole: as a consequence a novel design environment currently under development is aimed at supporting the design of flashbased mass-memory device for space applications.
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