Design and optimization of adaptable BCH codecs for NAND flash memories

Fabiano, Michele; Indaco, Marco; Carlo, Stefano Di; Prinetto, P.

doi:10.1016/j.micpro.2013.03.002

Cited by 12 publications

(8 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The single/multiple blocks read/write procedures were designed using FSM, and they have been implemented those procedures using HDL for target device. Also, the BCH code for NAND flash memory has been optimized in previous work [31] and the data-intensive application using FPGA has been performed in earlier researches [32,33].…”

Section: Review Of the Related Workmentioning

confidence: 99%

A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

Banerjee

Mukhopadhyay

2016

J Embedded Systems

View full text Add to dashboard Cite

Real-time multimedia data access plays an important role in electronic systems; as time goes by, with decrease in data processing speed and increase in communication time, storage time, and retrieval time, the overall response time increases for real-time applications. Therefore, in this paper, a novel real-time, fast, low-cost, system-on-chip (SoC) controller has been proposed and implemented where large volume of data can be efficiently stored and retrieved from flash memory cards. It is being implemented only using hardware description language (HDL) on a field programmable gate array (FPGA) chip without using any other on-board or external hardware resources or high-level languages. The entire controller architecture, in a single chip, contains five different modules and is designed using finite state machine (FSM)-based approach. The modules are card initialization module (CINM), idle module (IM), card read module (CRM), card write module (CWM), and decision module (DM). The architecture is completely synthesized for Spartan 3E xc3s500e-4-fg320 FPGA with only 5% of the total logic utilization. The experimental results tested for microSD, SD, and SDHC cards of different size, and these show that the architecture uses less hardware and clock cycles for card initialization and single/multiblock read/write procedure.

show abstract

Section: Review Of the Related Workmentioning

confidence: 99%

A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

Banerjee

Mukhopadhyay

2016

J Embedded Systems

View full text Add to dashboard Cite

show abstract

“…The ECC subsystem exploited in this article implements the adaptable BoseChaudhuri-Hocquenghem (BCH) ECC architecture presented by Fabiano et al [2013]. BCH codes belong to the larger class of cyclic codes, which have efficient decoding algorithms due to their strict algebraic architecture [Bose and Ray-Chaudhuri 1960].…”

Section: Characterization Of An Adaptive Ecc Subsystemmentioning

confidence: 99%

“…Mainly, these devices enable speed/power consumption optimization by changing the memory bus interface speed (e.g., Micron MT29F16G08ABABA NAND Flash) and the storage model (i.e., choosing SLC or MLC writing schemes [Samsung 2012]). Concurrently with these solutions, several researchers focused on the optimization of the flash write algorithms [Liu et al 2012] to guarantee a performance-reliability tradeoff and on the use of adaptive ECC schemes to trade off storage space and performance for higher error correction capability [Chen et al 2009;Fabiano et al 2013]. Some studies also investigated how mechanisms that enable applications to store data approximately also enable improved performance whenever high-precision storage is not required [Sampson et al 2013].…”

Section: Introductionmentioning

confidence: 99%

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Bertozzi

Carlo

Galfano

et al. 2015

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications. However, when considering data and code storage in non-volatile memories (NVMs), such as NAND flash memories, reliability and performance become a serious concern for systems’ designer. Designing NAND flash based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity. This is clearly in contrast with the request for run-time reconfigurability, adaptivity, and resource optimization in nowadays computing systems. There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated trade-off point in the performance-reliability optimization space. This is supported by the possibility of tuning the NAND flash memory performance, reliability and power consumption acting on several tuning knobs such as the flash programming algorithm and the flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory to clearly understand the effect the combined tuning of these parameters have on the full NVM sub-system. This paper performs a comprehensive quantitative analysis of the benefits provided by the run-time reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming circuitry coupled with run-time adaptation of the ECC correction capability. The full nonvolatile memory (NVM) sub-system is taken into account, starting from the characterization of the low level circuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide the readers a clear figure of the benefit this combined adaptation would provide at the system level

show abstract

“…• adaptability, i.e., a fixed correction capability ECC schema versus a variable one can be chosen [21], [26];…”

Section: A System Configuratormentioning

confidence: 99%

Ef<sup>3</sup>S: An evaluation framework for flash-based systems

Carlo

Galfano

Indaco

et al. 2013

2013 IEEE 19th International on-Line Testing Symposium (IOLTS)

Self Cite

View full text Add to dashboard Cite

NAND Flash memories are gaining popularity in the development of electronic embedded systems for both consumer and mission-critical applications. NAND Flashes crucially influence computing systems development and performances. EF 3 S, a framework to easily assess NAND Flash based memory systems performances (reliability, throughput, power), is presented. The framework is based on a simulation engine and a running environment which enable developers to assess any application impact. Experimental results show functionality of the framework, analysing several performance-reliability tradeoffs of an illustrative system.

show abstract

Design and optimization of adaptable BCH codecs for NAND flash memories

Cited by 12 publications

References 15 publications

A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

A low cost and fast controller architecture for multimedia data storage and retrieval to flash-based storage device

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Ef<sup>3</sup>S: An evaluation framework for flash-based systems

Contact Info

Product

Resources

About