Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Bertozzi, Davide; Carlo, Stefano Di; Galfano, Salvatore; Indaco, Marco; Olivo, P.; Prinetto, P.; Zambelli, Cristian

doi:10.1145/2629562

Cited by 10 publications

(6 citation statements)

References 16 publications

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“…Bertozzi et al [10] observe that designing NAND flashbased systems based on worst-case scenarios leads to a waste of resources in terms of performance, power consumption, and storage capacity, thus, they exploit runtime reconfigurability to support differentiated access modes in flash memory controller, this paper proposes to combine an adaptable memory programming algorithms and adaptable ECC for providing trade-off between performance, reliability, and power.…”

Section: B Model-based Techniques For Optimizing Reliability Of Nand Flash Memorymentioning

confidence: 99%

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Zhang

et al. 2019

IEEE Access

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NAND flash memory is widely used in various computing systems. However, flash blocks can sustain only a limited number of program/erase (P/E) cycles, which are referred to as the endurance. On one hand, in order to ensure data integrity, flash manufacturers often define the maximum P/E cycles of the worst block as the endurance of flash blocks. On the other hand, blocks exhibit large endurance variations, which introduce two serious problems. The first problem is that the error correcting code (ECC) is often over-provisioned, as it has to be designed to tolerate the worst case to ensure data integrity, which causes longer decoding latency. The second problem is the underutilized block's lifespan due to conservatively defined block endurance. Raw bit error rate (RBER) of most blocks have not arrived the allowable RBER based on the nominal endurance point, which implies that the conventional P/E cycle-based block retirement policies may waste large flash storage space. In this paper, to exploit the storage capacity of each flash block, we propose an RBER-aware lifetime prediction scheme based on machine learning technologies. We consider the problem that the model can lose prediction effectiveness over time and use incremental learning to update the model for adapting the changes at different lifetime stages. At run time, trained data will be gradually discarded, which can reduce memory overhead. For evaluating our purpose, four wellknown machine learning techniques have been compared in terms of predictive accuracy and time overhead under our proposed lifetime prediction scheme. We also compared the predicted values with the tested values obtained in the real NAND flash-based test platform, and the experimental results show that the support vector machine (SVM) models based on our proposed lifetime prediction scheme can achieve as high as 95% accuracy for flash blocks. We also apply our proposed lifetime prediction scheme to predict the actual endurance of flash blocks at four different retention times, and the experimental results show that it can significantly improve the maximum P/E cycle of flash blocks from 37.5% to 86.3% on average. Therefore, the proposed lifetime prediction scheme can provide a guide for block endurance prediction.

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Section: B Model-based Techniques For Optimizing Reliability Of Nand Flash Memorymentioning

confidence: 99%

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Zhang

et al. 2019

IEEE Access

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“…This value represents 35% of the guaranteed retention time at 70°C in order to bridge the 280% gap between the guaranteed retention times at 70°C and 30°C in 8 steps. The increment values for the status register can be calculated based on (1).…”

Section: Time Integration Of Temperature Impact On Thementioning

confidence: 99%

“…As a matter of fact, the allowed number of cumulated P/E cycles can be augmented as long as a mechanism is provided to cope with the resulting retention time reduction. Besides the use of stronger error correcting codes [1], an efficient approach to deal with an insufficient retention time is to periodically check and refresh the stored data [2][15] [18] [19]. A refresh operation can be executed inplace by injecting only the missing amount of charge in the floating gates of the target flash memory cells or by reprogramming the concerned data at a different physical location [2] [3].…”

Section: Introductionmentioning

confidence: 99%

Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps

Seif

Farjallah

Badets

et al. 2017

2017 22nd IEEE European Test Symposium (ETS)

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International audienceIncreasing the number of bits per cell and technology scaling are ways to reduce the cost per gigabyte of flash memories and solid-state drives (SSDs). Unfortunately, this trend has a negative impact on data retention capability and cycling endurance. Periodic data refresh allows dealing with a reduced retention time and, indirectly, may be used to improve cycling endurance. A worst case data refresh frequency is not optimal in the presence of important temperature variations as it may become unnecessarily pessimistic and alter the SSD response latency and energy consumption. Here, a flexible data refresh methodology is proposed based on approximations of the Arrhenius-curves employed to describe the temperature impact on the retention capability of flash memories. These approximations may be implemented with the help of a small module called A-timer. For an asymmetric temperature distribution between 30°C and 70°C, it is estimated that the refresh frequency can be reduced by more than 63× and almost 3× for respectively charge detrapping and SILC failure mechanisms

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“…The need for strong ECCs may be reduced by containing the raw bit error rate (RBER). Besides technological fixes or solutions based on improved read and write algorithms [1][4] [13], the RBER can be tempered if the stored data are periodically refreshed [2][13] [14] [17]. A refresh operation can be executed in-place by injecting only the missing amount of charge into the floating gate of the flash memory cells or by relocating the data to a different physical location [2] [3].…”

Section: Introductionmentioning

confidence: 99%

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh

Farjallah¹,

Armani²,

Gherman³

et al. 2019

Microelectronics Reliability

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A recent large-scale study revealed that the uncorrectable bit error rates in data center solid-sate drives (SSDs) may fall far below the JEDEC standard recommendations. Here, a technique is proposed to improve the tolerated raw bit error rate (RBER) based on the observation that (a) a small SSD ratio may have a much higher RBER than the rest and (b) the RBER is dominated by the retention error rate. Instead of employing stronger but costly error-correcting codes an approach is used to estimate the remaining retention time, i.e., the reliable data storage time, of flash memory pages. This estimation can be performed each time a memory page is read based on the number of detected retention errors and the elapsed time since data was programmed. The fact that the estimated remaining retention time is smaller than a maximum time interval before the next read and check operation is an indication that data needs to be refreshed. It is estimated that the tolerated RBER can be increased by up to 35× over a storage period of 3 years if the stored data are checked on a monthly basis and refreshed only if necessary. The proposed technique has the ability to adapt the average time between refresh operations to the actual RBER. Maximum refresh time reductions of about 12x are reported as compared to systematic refresh schemes.

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Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Cited by 10 publications

References 16 publications

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh

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