Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps

Abstract

International audienceIncreasing the number of bits per cell and technology scaling are ways to reduce the cost per gigabyte of flash memories and solid-state drives (SSDs). Unfortunately, this trend has a negative impact on data retention capability and cycling endurance. Periodic data refresh allows dealing with a reduced retention time and, indirectly, may be used to improve cycling endurance. A worst case data refresh frequency is not optimal in the presence of important temperature variations as it may become unnecessarily pessimistic and alter the SSD response latency and energy consumption. Here, a flexible data refresh methodology is proposed based on approximations of the Arrhenius-curves employed to describe the temperature impact on the retention capability of flash memories. These approximations may be implemented with the help of a small module called A-timer. For an asymmetric temperature distribution between 30°C and 70°C, it is estimated that the refresh frequency can be reduced by more than 63× and almost 3× for respectively charge detrapping and SILC failure mechanisms

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh

“…The retention age 𝑡 𝐴𝐺𝐸 can be calculated as the difference between a timestamp associated to the page being accessed and the current state of the timer used to provide timestamps [6]. A single timestamp may be used to characterize the programing time of all pages in a flash memory block [18]. The resulting storage overhead of the timestamp table is significantly smaller than in the case of other metadata structures such as the remapping table of the flash translation layer [18].…”

“…A single timestamp may be used to characterize the programing time of all pages in a flash memory block [18]. The resulting storage overhead of the timestamp table is significantly smaller than in the case of other metadata structures such as the remapping table of the flash translation layer [18].…”

“…Check operations as described in Algorithm 1 can be imposed periodically via warnings triggered by a conventional or temperature aware timer [18]. Since such checks can also be associated to functional read operations, frequently accessed pages may be skipped during the periodical checks triggered by the timer.…”

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics

“…A single timestamp may be used to characterize the programing time of all pages in a flash memory block [13]. The resulting storage overhead of the timestamp table is significantly smaller than in the case of other metadata structures such as the remapping table of the [19].…”

“…For example, if one considers M=10, =1, equal to 3 years and equal to 1 month, the resulting storage overhead is 288 bits. This is negligible compared to the overhead of the FTL remapping table whose size is measured in megabytes [19].…”