A practical approach of transferring a hexagonal array of nanosized pores produced in porous alumina into silicon and other substrates is discussed. The alumina pores have dimensions of 25–250 nm pore diameters and 50–300 nm pore spacings depending on the anodization conditions used. The characteristics of the alumina pores and the alumina–silicon interface are studied for different substrate materials and anodizing conditions. The unique structure of the barrier layer allows for the alumina to be directly used as an etch mask for pattern transfer into the silicon substrate.

A nanoporous alumina template made from a multilayer metal film structure has been developed that allows for the in situ removal of the electrically insulating alumina barrier layer, exposing a Pt electrode at the pore bases. This barrier-free nanoporous system is of great use for dc electrodeposition of a wide variety of materials in the alumina pores. This work in particular describes the development of a multilayer thin film precursor consisting of a Si substrate with thin Pt and Ti and a thicker Al layer in that order. After the Al is anodized, producing the porous alumina, the resulting TiO 2 is selectively removed at the base of the alumina pores exposing the Pt electrode. The metals in the precursor perform different roles in the fabrication and allow the alumina template to be fabricated directly on the final substrate with no film transfer technique involved. This allows Si to be used as the substrate, which could then include electronic circuitry. Several techniques are used to analyze the resulting template.

In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

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