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Quantum Dot Cellular Automata (QCA) is a rising innovation which seems to be a good competitor for the next generation of digital systems and widely utilized as a part of advanced frameworks. It is an appealing substitute to ordinary CMOS innovation because of diminutive size, faster speed, extremely scalable feature, ultralow power consumption and better switching frequency. The realization of quantum computation is not possible without reversible logic. Reversible logic has enlarged operations in quantum computation. Generally reversible computing is executed when system composes of reversible gates. It has numerous fields of use as applied science, quantum dot cellular automata as well as low power VLSI circuits, low power CMOS, digital signal processing, computer graphics. In this paper, the quantum implementation of primitive reversible gate has been presented. The proposed gates have been designed and simulated using QCADesigner.

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Traditional lithography based VLSI architecture expanded to optimize higher scale integration and low powered computing of semiconductor components. This tend encounter severe challenges of short channel issue, tunneling and variation of doping. Quantum Dot Cellular Automata (QCA) is an esteemed nano-scale technology and a better substitute of Complementary Metal Oxide Semiconductor (CMOS) for it's transformation technique and computation method. Information-lossless or reversible logic circuits has divers precise utilization in communications, digital signal processing (DSP), computer graphics also in quantum computation. This paper presents the systematic model of Peres gate (PG) and R gate in QCA and CMOS. To simulate and verify the proposed design QCADesigner and Microwindlite, widely used simulation tools are used. Those proposed design has a promising future and can be used in modeling complex computing structure and nano-scale based low power consumption information processing structure.

Quantum dot cellular automaton (QCA) are dominant nanotechnology which has been used extensively in digital circuits and systems. It is a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology with many enticing features such as high-speed, low power consumption and higher switching frequency than transistor based technology. The code converters are the basic unit for transformation of data to execute arithmetic processes. In this paper, QCA based 2-bit binary-togray; 3-bit binary-to-gray and 4-bit binary-to-gray code converter have been proposed. The proposed design reduces the number of cells, area and raises switching speed. The simulations are completed using QCADesigner and Microwindlite tool which is widely used for simulation and verification.

Quantum-dot cellular automata (QCA) is the beginning of novel technology and is capable of an appropriate substitute for orthodox semiconductor transistor technology in the nanoscale extent. A competent adder and subtractor circuit can perform a substantial function in devising arithmetic circuits. The future age of digital techniques will exercise QCA as preferred nanotechnology. The QCA computational procedures will be simplified with an effective full adder and subtractor circuit. The deficiencies of variations and assembly still endure as a setback in QCA based outlines, and being capricious and inclined to error is the limitation of these circuits. In this study, a new full adder and subtractor design using unique 3-input XOR gate with cells redundancy is proposed. This designs can be utilized to form different expedient QCA layouts. The structures are formed in a single layer deprived of cross-wiring. Besides, this study is directed to the analysis of the functionality and energy depletion possessions of the outlined full adder and subtractor circuits. For the first time, QCADesigner-Energy (QD-E) version 2.0.3 tool is utilized to find the overall depleted energy. The attained effects with QCADesigner have verified that the outlined design has enhanced functioning in terms of intricacy, extent, and latency in contrast to the earlier designs. Moreover, the redundant form of full adder and subtractor has uncomplicated and robust arrangement competing typical styles.

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