International audienc

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This paper introduces an innovative design of a low-pass (LP) negative group delay (NGD) integrated circuit (IC) in 180-nm CMOS technology. The LP-NGD circuit is an inductorless topology constituted by RC-network with CMOS metal-insulator-metal (MIM) capacitor and poly gate resistor. The design methodology is illustrated by considering the chip layout process. Then, the first run simulation is performed with the design rule check (DRC) and 2.5 mm × 2.2 mm layout versus schematic (LVS) approaches. The feasibility of the CMOS LP-NGD IC circuit implementation is validated with chip-on-board (CoB). The proof of concept (PoC) of the LP-NGD miniaturized circuit was tested in both S-parameter and time-domain. As expected, the calculated, simulated and experimented results of CoB showing NGD of about -10 ns over 12 MHz and -10 dB attenuation is confirmed. Moreover, time-domain investigations were also performed to show the feasibility of generating pulse and arbitrary waveform signal time-advance through the designed and fabricated LP-NGD CoB prototypes.