This paper describes a 0.11 p m CMOS technology with high-reliable copper and very-low-k (VLK) (kc2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 p m gate transistor, and 2.2 p mz 6T-SRAh4 cell are realized by using KrF 248nm lithography, opticalproximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63mA/ p m and 0.281nN p m are realized for nMOSFET and pMOSFET with 0.11 p m gate, respectively. Propagation delay of 2-input NAND with the copperlhybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 fi m CMOS technology with copper/FSG interconnects.
ABSTRACrA new exposure method for the depth of focus enhancements without using the off axis filter has been developed. It makes KrF excimer laser (248nm) lithography to a robust mass production tool beyond 2nd generation of 64MDRAM class devices.With this new exposure method, the depth of focus for O.35pin geometries, which includes the vertical and the oblique direction images, can be enlarged more than 45%. The common depth of focus between the line images and the space images can not be obtained with the quadrupole and the ring illumination methods for the actual sub-O.3Ojim rule devices. Even for these devices, over 1.1im depth of focus can be achieved with this newly developed exposure method.
We demonstrate applications of alternating phase shift mask (Alt-PSM) techniques to ArF excimer laser lithography with a numerical aperture of 0.6 and a coherence factor of 0.3. A 0.10 µm line-&-space (L/S) pattern was fabricated using a single-layer resist and a 0.09 µm L/S pattern was fabricated using a silylation resist. However, the process window was smaller for the silylation resist than for the single-layer resist over the 0.10–0.13 µm L/S range. The maximum depth of focus (DOF) values were approximately 0.3, 0.5, and 0.9 µm for 0.10, 0.11, and 0.13 µm L/S patterns, respectively, for the single-layer resist. From exposure dose-DOF-tree analysis, we estimated the inclusive process margin including the critical dimension difference, the DOF, the dose margin, and the phase error. Assuming that the usable DOF is larger than 0.5 and 0.6 µm for 0.11 and 0.13 µm L/S patterns, respectively, the inclusive process margin for the single-layer resist is poor in comparison with future predictions.
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