In this work we present results of capacitance measurements monitoring variations of the interconnect process. The measurements are compared with a 3D-simulation. The compadson shows that for a standard parasitics extraction the capacitance can be underestimated by up to -30% c o m p d to measured results, In order to overcome this discrepancy, in our extraction, we consider fill structures, line widening for yield enhancement and process specific effects such as opticaal proximity and highly trapezoidal uoss section of the conductom. This Beads to good agreement between measured and extracted results. We PISO evaluate in detail the contribution of each effect to the total capacitance.
Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.
-Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.
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