Measurement and simulation of interconnect capacitance variations

Sauter, Stéfan A.; Rein, Andrew; Frerichs, Martin R.; Schmitt‐Landsiedel, D.; Thewes, R.; Weber, W.

doi:10.1109/iwstm.2000.869313

Cited by 3 publications

(1 citation statement)

References 4 publications

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“…This section presents the results of a comparison between measurements and standard layout based extracted data for small test structures that have been fabricated in a quarter micron CMOS technology [12].…”

Section: Measurement and Extraction A Case Studymentioning

confidence: 99%

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Frerichs

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

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-Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.

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Section: Measurement and Extraction A Case Studymentioning

confidence: 99%

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Frerichs

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

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show abstract

Interconnect Characterization: Accuracy, Methodology, and Practical Considerations

Elsayed

Farhang

Yip

2008

IEEE Trans. Semicond. Manufact.

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Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling

Frerichs

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.

show abstract

Measurement and simulation of interconnect capacitance variations

Cited by 3 publications

References 4 publications

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Interconnect Characterization: Accuracy, Methodology, and Practical Considerations

Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling

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