Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling

Abstract

Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.