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SymTA/S is a system-level performance and timing analysis approach based on formal scheduling analysis techniques and symbolic simulation. The tool supports heterogeneous architectures, complex task dependencies and context aware analysis. It determines system-level performance data such as end-to-end latencies, bus and processor utilization, and worst-case scheduling scenarios. SymTA/S furthermore combines optimization algorithms with system sensitivity analysis for rapid design space exploration. This paper gives an overview of the current research interests in the SymTA/S project.

ultiprocessor system on chip designs use complex on-chip networks to integrate multiple programmable processor cores, specialized memories, and other intellectual property (IP) components on a single chip. MpSoCs have become the architecture of choice in industries such as network processing, consumer electronics, and automotive systems. Their heterogeneity inevitably increases with IP integration and component specialization, which designers use to optimize performance at low power consumption and competitive cost. Figure 1 shows an example MpSoC, the Viper processor for multimedia applications. 1 Based on the Philips Nexperia platform, it includes many key components that are either reused or supplied externally, such as the MIPS and TriMedia processor cores. Tomorrow's MpSoCs will be even more complex, and using such IP library elements in a "cut-andpaste" design style is the only way to reach the necessary design productivity. Systems integration is becoming the major challenge in MpSoC design. Complex hardware and software component interactions pose a serious threat to all kinds of performance pitfalls, including transient overloads, memory overflow, data loss, and missed deadlines. The International Technology Roadmap for Semiconductors, 2001 Edition, (http:// public.itrs.net/files/2001itrs/design.pdf) names system level performance verification as one of the top three codesign issues. PERFORMANCE SIMULATION: CAN IT GET THE JOB DONE? Simulation is state of the art in MpSoC performance verification. Tools such as Mentor Graphics' Seamless-CVE or Axys Design Automation's Max-Sim support cycle-accurate cosimulation of a complete hardware and software system. The cosimulation times are extensive, but developers can use the same simulation environment, simulation patterns, and benchmarks in both function and performance verification. Simulation-based performance verification, however, has conceptual disadvantages that become disabling as complexity increases. MpSoC hardware and software component integration involves resource sharing that is based on operating systems and network protocols. Resource sharing results in a confusing variety of performance runtime dependencies. For example, Figure 2 shows a CPU subsystem executing three processes. Although the operating system activates P 1 , P 2 , and P 3 strictly periodically (with periods T 1 , T 2 , and T 3 , respectively), the resulting execution sequence is complex and leads to output bursts. As Figure 2 shows, P 1 can delay several executions of P 3. After P 1 completes, P 3-with its input buffers filled-temporarily runs in burst mode with the exe-A new technology uses event model interfaces and a novel event flow mechanism that extends formal analysis approaches from real-time system design into the multiprocessor system on chip domain.

We consider complex embedded systems, where large, heterogeneous sets of communicating tasks are executed on heterogeneous multi-processor / multi-bus architectures with RTOSes and bus-arbitration. Examples include systems-on-chip for mobile communication, multimedia platforms or distributed automotive control systems. In such systems, data-dependent task execution times and preemption lead to data jitter and bursts, and consequently to sophisticated run-time interdependencies between tasks. Reliable validation of timing constraints in such systems can no longer be achieved through simulation due to incomplete corner-case coverage, but instead requires formal performance analysis. Existing system-level performance analysis techniques assume that the completion of one task immediately leads to the activation of a dependent task. However, activation dependencies in realistic embedded applications are often more complex, including multirate data dependencies, multiple activating inputs, cyclic dependencies or conditional communication. In these cases, existing performance analysis techniques are not directly applicable. In this paper, we focus on the calculation of activation timing in the presence of complex task dependencies. These calculations are then integrated into a system-level performance analysis framework for heterogeneous architectures. Using a larger example, we demonstrate how performance analysis allows rapid design-space exploration to optimize the implementation of realistic embedded applications while satisfying all critical timing constraints.

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