A formal approach to mpsoc performance verification

Abstract

ultiprocessor system on chip designs use complex on-chip networks to integrate multiple programmable processor cores, specialized memories, and other intellectual property (IP) components on a single chip. MpSoCs have become the architecture of choice in industries such as network processing, consumer electronics, and automotive systems. Their heterogeneity inevitably increases with IP integration and component specialization, which designers use to optimize performance at low power consumption and competitive cost. Figure 1 shows an example MpSoC, the Viper processor for multimedia applications. 1 Based on the Philips Nexperia platform, it includes many key components that are either reused or supplied externally, such as the MIPS and TriMedia processor cores. Tomorrow's MpSoCs will be even more complex, and using such IP library elements in a "cut-andpaste" design style is the only way to reach the necessary design productivity. Systems integration is becoming the major challenge in MpSoC design. Complex hardware and software component interactions pose a serious threat to all kinds of performance pitfalls, including transient overloads, memory overflow, data loss, and missed deadlines. The International Technology Roadmap for Semiconductors, 2001 Edition, (http:// public.itrs.net/files/2001itrs/design.pdf) names system level performance verification as one of the top three codesign issues. PERFORMANCE SIMULATION: CAN IT GET THE JOB DONE? Simulation is state of the art in MpSoC performance verification. Tools such as Mentor Graphics' Seamless-CVE or Axys Design Automation's Max-Sim support cycle-accurate cosimulation of a complete hardware and software system. The cosimulation times are extensive, but developers can use the same simulation environment, simulation patterns, and benchmarks in both function and performance verification. Simulation-based performance verification, however, has conceptual disadvantages that become disabling as complexity increases. MpSoC hardware and software component integration involves resource sharing that is based on operating systems and network protocols. Resource sharing results in a confusing variety of performance runtime dependencies. For example, Figure 2 shows a CPU subsystem executing three processes. Although the operating system activates P 1 , P 2 , and P 3 strictly periodically (with periods T 1 , T 2 , and T 3 , respectively), the resulting execution sequence is complex and leads to output bursts. As Figure 2 shows, P 1 can delay several executions of P 3. After P 1 completes, P 3-with its input buffers filled-temporarily runs in burst mode with the exe-A new technology uses event model interfaces and a novel event flow mechanism that extends formal analysis approaches from real-time system design into the multiprocessor system on chip domain.

Analyzing composability of applications on MPSoC platforms

“…Alternative methods have been proposed for analyzing task performance and resource sharing. A formal approach to verification of MPSoC performance has been proposed in [20]. Use of realtime calculus for schedulability analysis was proposed in [23].…”

Modeling and Validating Distributed Embedded Real-Time Systems with VDM++

“…Event model interfaces (EMIFs) or event model adaptor functions (EAFs) are used so that classical scheduling analysis techniques can be safely applied at the abstract component level. It is claimed that this approach leads to both hard and tight results [84].…”

“…Similarly, SymTA/S can deal with complex task interdependencies that are hard if not impossible to model in Modular Performance Analysis. An overview of SymTA/S is provided in [84]. The tool is available, as a commercial product, from http://www.symtavision.com.…”

Analysis and Optimisation of Hierarchically Scheduled Multiprocessor Embedded Systems

“…Over the time, extensions have been offered to response time analysis for fixed priority scheduling by taking into account task synchronisation [Sha90], arbitrary deadlines [Leh90], precedence constraints between tasks [Pal99] and tasks with varying execution priorities [Gon91], arbitrary release times [Aud93], [Tin94c], tasks which suspend themselves [Pal98], tasks running on multiprocessor systems [Tin94a], [Pal98], etc. In [Ric02] and [Ric03], the authors model the multiprocessor heterogeneous systems as components that communicate through event streams and propose a technique for integrating different local scheduling policies based on such event-model interfaces. Another compositional approach is presented in [Wan05], where the authors propose real-time interfaces and a component model that support incremental design of real-time systems.…”