High-defect density in thermodynamics driven directed self-assembly (DSA) flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high-volume manufacturing. The major questions raised in this regard are: (1) What is the intrinsic level of DSA-induced defects? (2) Can we isolate the DSA-induced defects from the other processes-induced defects? (3) How much do the DSA materials contribute to the final defectivity and can this be controlled? (4) How can we understand the root causes of the DSA-induced defects and their kinetics of annihilation? (5) Can we have block copolymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low-defect levels? We address these important questions and identify the issues and the level of control needed to achieve a stable DSA defect performance.

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Double patterning is the best technique which allows 193nm immersion lithography to anticipate the 32 nm node, before EUV lithography. The final device pattern is formed by two independent patterning steps where the dense pitch is doubled. This allows printing each patterning step with higher k1 imaging factor.In this paper we present the overlay and CD budget applied to a double patterning (DP) technique for the definition of a 32nm technology node device, using an immersion scanner tool. A balance among different factors which affects the final CD of the device is necessary to optimize the imaging and the alignment performances of the exposure tool. A preliminary activity is also necessary to choose the most suitable mask splitting strategy. Adopting a single mask, which is exposed twice with the appropriate shift -the final pitch -, makes the overlay between the two exposures less critical than splitting the complementary layouts on two different masks. Finally, the CD uniformity of the pooled distributions from the two exposures is evaluated in order to define the requested tool performances in terms of overlay, CD control and metrology.

As Moore's law drives the semiconductor industry to tighter specifications, challenges are becoming real for overlay metrology. A lot of work has been done on the metrology tool capability to improve single-tool precision, tool-to-tool matching and Tool-Induced Shift (TIS) variability. But nowadays these contribute just a small portion of the Overlay Metrology Error (approximately 10% for 90nm technology). Unmodeled systematic, scanner noise and process variation are becoming the major contributors. In order to reduce these effects, new target design was developed in the industry, showing improvements in performance. Precision, Residual analysis, DI/FI (Develop Inspection / Final Inspection) bias and Overlay Mark Fidelity (OMF) are common metrics for measurement quality. When we come to measurement accuracy, we do not have any direct metric to qualify targets. In the current work we evaluated the accuracy of different AIM (developed by Kla-Tencor) and Frame-In-Frame (FIF) targets by comparing them to reference "SEM" targets. The experiment was conducted using a special designed 65nm D/R reticle, which included various overlay targets. Measurements were done on test wafers with resist on etched poly printed on 248nm scanner. The results showed that, for this "straight-forward" application, the best accuracy performance was achieved by the Non Segmented (NS) AIM target and was estimated in the order of 1.5 nm site-to-site. This is slightly more accurate than hole-based target and far more than NS FIF target in this particular case. When using the non-accurate NS FIF target, correctable parameters and maximum overlay prediction error analysis, showed up to 24nm overlay error at the edge of the wafer. We also showed that part of this accuracy error can be attributed to the non-uniformity of BARC deposition.