This paper presents a drain leakage current I Leak comparative study between conventional and the novel SOI MOSFET structure, known as Diamond transistor, operating from room temperature up to 300 o C, regarding the same dimensions, aspect ratio, area and bias conditions, by using 3-D numerical simulations. It is shown that Diamond SOI nMOSFET presents larger drain leakage current (composed mainly by electrons) than conventional counterpart, due to its higher longitudinal electric field, which it depends on the hexagonal geometric shape of the gate-source/drain interfaces geometrics shapes. As far as α is close to 180 o , the Diamond I Leak is practically the same as conventional SOI MOSFET.
In this work we present a simple analytical model to study the Zero Temperature Coefficient (ZTC) bias point in FinFETs operating from room temperature up to 573 K. Three-dimensional simulations are carried out and compared with experimental results to qualify the results.
This paper presents the electric behavior of Δ-channel SOI nMOSFET transistors (triangular channel), as a function of the channel geometric dimensions, such as the channel length (L) and the internal angle (θ) of the triangular structure, in the drain leakage current (IDleak) behavior, for these devices operating since room temperature up to 300ºC. Through three-dimensional numeric simulations it was observed that IDleak is composed mainly by electrons, in all analyzed devices operating at high temperatures. Besides that, as L reduces, it was noticed that IDleak increases. However, for smaller angles θ, result smaller IDleak values, when the transistors are operating at same bias and temperature conditions.
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