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Abstract. Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach.

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CATHEDRAL-2nd is a new synthesis environment, intended to be the follow-up of our current CATHEDRAL-I1 approach. It is tuned towards the mapping of complex medium sample rate DSP applications onto flexible microcoded architectures. An important novel feature, is the increase in architectural freedom. As opposed to the formerly predefined limited set of execution units (EXUs) in CATHEDRAL-11, the system supports more flexibility in the composition of EXUs. The paper treats the impact of this feature on scheduling, hardware assignment and memory management.