Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment

Lanneer, D.; Depuydt, Francis; Pauwels, Marc; Catthoor, Francky; Goossens, Gert; Man, H. De

doi:10.1007/978-1-4615-3966-7_2

Cited by 20 publications

(5 citation statements)

References 4 publications

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“…Second, the PRISM-II execution model successfully addresses the issue of executing loops with dynamic loop counts. Third, the proposed execution model possesses several important advantages over existing models proposed in traditional high-level synthesis architectures [18][19][20] and [21]. Traditional high-level synthesis architectures utilize centralized controllers that, in turn, impose strict sequential execution of instructions, resulting in the failure to exploit potential fine-grain parallelism.…”

Section: Model Of Executionmentioning

confidence: 99%

“…Trickey [18] presents a 'hardware' compiler that translates high-level behavioral descriptions of digital systems, in Pascal, into hardware, subject to user-specified cost function. Lanneer and colleagues [19] report the CATHEDRAL high-level synthesis environment for automated synthesis of IC architectures for realtime, digital signal processing. IBM's HIS system [20] translates a behavioral description of a synchronous digital system specified in VHDL into a resulting design consisting of a finite state machine and a datapath, both described in the output language BDL/ CS.…”

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confidence: 98%

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An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

Ghosh

1997

Journal of Network and Computer Applications

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Section: Model Of Executionmentioning

confidence: 99%

mentioning

confidence: 98%

An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

Ghosh

1997

Journal of Network and Computer Applications

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“…No architecture description is needed, though user guidance with the aid of pragma statements is generally desirable. Its successor, the Cathedral-2nd compiler introduces more freedom by allowing a combination ofpredefined execution units with user defined custom execution units, [27].…”

Section: Custom Processors: C-to-silicon Cathedralli/2ndmentioning

confidence: 99%

“…A second (and third) level of memory hierarchy is provided by on-chip and off-chip background memory. The CATHEDRAL-III synthesis environment maps onto a similar architecture, [30] [27].…”

Section: High Speed Data Path Processors: Hypermentioning

confidence: 99%

Synthesis for real time systems: Solutions and challenges

Verbauwhede

Rabaey

1995

Journal of VLSI Signal Processing

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Abstract.A real time system typically combines a variety of implementation technologies and hardware architectures. Deciding how to partition the system and selecting an architectural technology for the sub-systems is by no means a trivial task. These architectural decisions, which can have a major impact on the quality and performance of the final implementation, have to be made at the early stages in the design process, when the impact of the decisions is unclear and can only be quantified using some primitive measures.In this paper, we present our vision on how a next generation of design environment can aid the designer in this decision process. We first identify the problems of designing a heterogeneous real time system by walking through the design process of a complex speech recognition system. Based on this analysis, we propose a system design methodology build on top of current synthesis tools. Today, DSP synthesis tools are application and/or architecture specific, covering subparts of the application once the partitioning is made. To make them useful in the proposed methodology, a unified view on the underlying architecture assumptions is needed. Secondly, good decision making requires an "as-good-as-possible" estimation of the implications of the decision. Therefore, it is important that current manual estimation be enlarged by high level estimation and performance analysis tools.The HYPERSPACE environment, which is currently under development, therefore, consists of three complementary components: a set of architecture specific compilers, a set of estimation and performance analysis tools and an architecture selection and partitioning framework, steered by the designer.

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“…Different approaches to reach the goal of fast and reliable implementations have been observed. General purpose high level design environments [2,3,4] try to synthesize circuits from a behavioral description which hides implementation details. The hardware synthesis process is done by allocating resources, mapping of operations to these resources, and subsequent scheduling.…”

Section: Hardware Generation Approachesmentioning

confidence: 99%

ComBox: library-based generation of VHDL modules

Vaupel

Grotker²,

Meyr³

VLSI Signal Processing, IX

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In this contribution we describe the automated generation of components for high throughput data-flow dominated VLSI-systems in digital communications. By means of a hierarchically organized library both behavioural models with high simulation efficiency and corresponding hardware genera tors that produce sophisticated VHDL descriptions are made easily accessible to the system designer. The structured approach allows the evaluation of the trade-offs between alternatives at each design step and guarantees a fast and reliable design flow towards hardware. The design environment ComBox enhances reusability and enables rapid implementation of complex systems starting from a system level description.

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Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment

Cited by 20 publications

References 4 publications

An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

Synthesis for real time systems: Solutions and challenges

ComBox: library-based generation of VHDL modules

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