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Germanium possesses higher electron and hole mobilities than silicon. There is a big leap, however, between these basic material parameters and implementation for high-performance microelectronics. Here we discuss some of the major issues for Ge metal oxide semiconductor field effect transistors ͑MOSFETs͒. Substrate options are overviewed. A dislocation reduction anneal Ͼ800°C decreases threading dislocation densities for Ge-on-Si wafers 10-fold to 10 7 cm −2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at ϳ6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for pϩ/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H 2 anneal for device performance is shown.

In search of a proper passivation for high-k Ge metal-oxide-semiconductor devices, the authors have deposited high-k dielectric layers on GeO2, grown at 350–450°C in O2. ZrO2, HfO2, and Al2O3 were deposited by atomic layer deposition (ALD). GeO2 and ZrO2 or HfO2 intermix during ALD, together with partial reduction of Ge4+. Almost no intermixing or reduction occurs during Al2O3 ALD. Capacitors show well-behaved capacitance-voltage characteristics on both n- and p-Ge, indicating efficient passivation of the Ge∕GeOx interface. The density of interface states is typically in the low to mid-1011cm−2eV−1 range, approaching state-of-the-art Si∕HfO2∕matal gate devices.

We have fabricated Cu2ZnSnSe4-CdS-ZnO solar cells with a total area efficiency of 9.7%. The absorber layer was fabricated by selenization of sputtered Cu10Sn90, Zn, and Cu multilayers. A large ideality factor of the order of 3 is observed in both illuminated and dark IV-curves, which seems to point in the direction of complex recombination mechanisms such as recombination through fluctuating potentials in the conduction and valence bands of the solar cell structure. A potential barrier of about 135 meV in the device seems to be responsible for an exponential increase of the series resistance at low temperatures, but at room temperature, the effect of this barrier remains relatively small. The free carrier density in the absorber is of the order of 1015 cm−3 and does not vary much as the temperature is decreased.

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The physical and electrical properties of Ge/GeO 2 /high-gate stacks, where the GeO 2 interlayer is thermally grown in molecular oxygen, are investigated. The high-layer ͑ZrO 2 , HfO 2 , or Al 2 O 3 ͒ is deposited in situ on the GeO 2 interlayer by atomic layer deposition. Detailed analysis of the capacitance-voltage and conductance-frequency characteristics of these devices provides evidence for the efficient passivation of the Ge͑100͒ surface by its thermal oxide layer. A larger flatband voltage hysteresis is observed in HfO 2 -based gate stacks, as compared to Al 2 O 3 gate stacks, which is possibly related to the more pronounced intermixing observed between the HfO 2 and GeO 2 .Inspired by the progress in the development of high-gate dielectrics for Si-based metal-oxide-semiconductor field-effect transistor ͑MOSFET͒ applications, 1 increasing attention is being focused on the feasibility of integrating high-gate dielectrics with germanium ͑Ge͒ because of its intrinsically higher mobility than silicon ͑Si͒. Electrical properties of several high-metal oxides deposited on Ge substrates have been recently reported, including HfO

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The authors show the implications that the free carrier trapping lifetime has on the capacitance-voltage (CV) characterization method applied to metal-oxide-semiconductor (MOS) structures. It is shown that, whereas the CV characterization method for deducing interface state densities works well for Si, the generally used frequency range of 100Hz–1MHz is much less adapted to GaAs MOS structures. Only interface trapping states in very small portions of the GaAs bandgap are measured with this frequency range, and mainly the very important midgap region is not properly probed. Performing an additional measurement at 150°C on GaAs MOS structures eliminates this problem.