High performance Ge pMOS devices using a Si-compatible process flow

Zimmerman, Paul; Nicholas, G.; Jaeger, B. De; Kaczer, B.; Stesmans, André; Ragnarsson, Lars‐Åke; Brunco, D.P.; Leys, Frederik; Caymax, Matty; Winderickx, G.; Opsomer, Karl; Meuris, Marc; Heyns, Marc

doi:10.1109/iedm.2006.346870

Cited by 127 publications

(98 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…For the silicon case, it is known [10] that halo implant increases hot-carrier (HC) degradation. To date, the most promising Ge results have been obtained using a Si-passivation layer where a few monolayers (MLs) of Si are epitaxially grown on the Ge surface immediately prior to gate stack formation [3], [4], [7], [8], [11]. In particular, it is interesting to note that Si-passivated Ge devices showed better electrical performance and reliability than silicon-nitride-passivated Ge devices, and Si-passivated Ge devices also showed better negative-bias-temperature-instability (NBTI) performance than their Si counterpart [12].…”

Section: Introductionmentioning

confidence: 99%

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

Maji

Crupi

Amat

et al. 2009

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-In this paper, a comprehensive study of hotcarrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: 1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; 2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and 3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement.Index Terms-Germanium, high-k, hot carrier (HC), impact ionization, negative bias temperature instability (NBTI), pMOSFET.

show abstract

Section: Introductionmentioning

confidence: 99%

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

Maji

Crupi

Amat

et al. 2009

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…It is confirmed that I s and I d were comparable down to around 10 -10 A/cm 2 in a wide range of the subthreshold region, providing an evidence of low leakage current in the drain junction originating in the formation of low leakage source/drain n + /p junctions by the gas phase doping. In addition, the fairly low D it of 1.36x10 12 cm -2 eV -1 was estimated from the subthreshold swing of 176 mV/dec.…”

Section: Ge Gate Stack Technologiesmentioning

confidence: 99%

“…The other direction is double layer gate stacks composed of high k layers and intentionally-formed interface control layers. A variety of interfacial layers such as SiO 2 /Si [10][11][12][13][14], GeO 2 [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], GeON [19,[31][32][33] and Ge 3 N 4 [16,[34][35][36][37] have already been reported. Although the introduction of interfacial low k layers could lead to the increase in EOT, superior interface properties to provide high inversion-layer mobility can be expected, as similar with the high k/SiO 2 /Si system.…”

Section: Introductionmentioning

confidence: 99%

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

et al. 2011

View full text Add to dashboard Cite

MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to III-V and Ge channels. However, one of the most critical issues for realizing Ge/III-V MOSFETs is gate insulator formation with superior MOS interface quality on Ge/III-V. In this paper, we focus on the possible solutions for gate stack technologies on Ge/III-V. As for Ge, GeO 2 /Ge interfaces have been regarded as promising. However, these interfaces have still employed thick GeO 2 layers. Recently, we have succeeded in thin EOT gate stacks with Ge oxide interfacial layers by using ECR plasma post oxidation. The high quality Al 2 O 3 /GeO x /Ge gate stacks were fabricated by exposing the ALD Al 2 O 3 /Ge structures to ECR oxygen plasma and oxidizing the Ge surface through the very thin ALD Al 2 O 3 layer. We present our recent results of the interface properties using this interface. As for InGaAs channels, we have also proposed a novel interfacial control technology utilizing InGaAs surface nitridation by ECR nitrogen plasma and successive post metallization annealing. This interfacial layer combined with an ECR sputtering SiO 2 or an ALD Al 2 O 3 gate insulator is shown to reduce D it down to low order of 10 11 cm -2 eV -1 . The physical origin of this D it reduction and the role of the nitridation are discussed.

show abstract

“…ZrO 2 [1], HfO 2 [2][3][4], and Al 2 O 3 [5]) are extensively discussed as alternative candidates for future complementary MOS technology due to the high carrier mobilities of germanium [6][7][8]. However, the growth of unstable and water-soluble germanium oxide during deposition and post-deposition annealing hinders the fabrication of competitive Ge-based MOS devices [9,10].…”

Section: Introductionmentioning

confidence: 99%

Impacts of Ti on electrical properties of Ge metal–oxide–semiconductor capacitors with ultrathin high-k LaTiON gate dielectric

et al. 2010

Appl. Phys. A

View full text Add to dashboard Cite

Ge Metal-Oxide-Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La 2 O 3 ratio, a suitable Ti/La 2 O 3 ratio of 14.7% results in a high relative permittivity of 24.6, low interfacestate density of 3.1 × 10 11 eV −1 cm −2 , and relatively low gate-leakage current density of 2.0 × 10 −3 A cm −2 at a gate voltage of 1 V.

show abstract

High performance Ge pMOS devices using a Si-compatible process flow

Cited by 127 publications

References 3 publications

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

Impacts of Ti on electrical properties of Ge metal–oxide–semiconductor capacitors with ultrathin high-k LaTiON gate dielectric

Contact Info

Product

Resources

About