This article describes the electrical and physical properties of polysilicon doped with novel N+ and P+ screen printed inks using a thermally activated process. Unique ink formulations for N and P type doping of silicon are evaluated in volume production in order to enable a low cost, high throughput process. Inks can be used with multiple substrate types and form factors. The concentrated doping source combined with thermal drive in and activation results in degenerately doped layers of polysilicon. Inks are semiconductor grade which is demonstrated by their use in fabricating high mobility, low leakage Thin Film Transistor (TFT) devices on 300 mm stainless steel substrates. Reproducible sheet resistance values (700 A polysilicon) can be engineered from levels typically ranging from 200 - 2000 ohm/sq. The additive approach substitutes the use of high capital cost ion implantation and lithography processes. The ink formulation results in screen printed widths capable of ranging from 100-300 um. As both N and P type layers can be printed adjacent to each other, it is critical to prevent cross doping using surface preparation techniques. Post doping cleaning of surfaces can be achieved in-situ or by plasma removal depending on process integration and product considerations. Reproducibility and uniformity data to demonstrate manufacturability in a production environment is shown. In summary, a simple, low cost, high throughput additive process based on proprietary inks that can be used in multiple product flows (CMOS TFT, Solar etc.) is demonstrated.

Laser crystallized CMOS TFTs were fabricated on thin 300 mm stainless steel substrates using novel coated silicon in a Printed Dopant PolySilicon (PDPS) process-flow [1]. Silicon ink will be a key building block for low-cost, continuous large-area coating or printing in very highvolume roll-to-roll manufacturing.RF devices with PECVD-equivalent TFT characteristics using semiconductor-grade inks are routinely fabricated using this process. This technology is foundational to RF (13.56MHz), display and integrated sensor system circuits on thin, large-area flexible and durable substrates.

Stainless steel substrates enable a combination of low cost, flexibility, durability, high processing temperatures, and sub-100 um thickness making it well suited for sheet based and roll-to-roll processing. NFC (13.56 MHz) based circuits using high performance polysilicon TFTs on steel sheets have been manufactured using a hybrid printed process in a production environment. The process scheme utilizes a hybrid, additive materials approach encompassing low cost manufacturing steps such as slot die coating and screen printing of silicon and dopant inks to enable a high throughput, low cost, manufacturing flow. This paper describes the approach for migrating from a sheet-based hybrid process flow to a R2R-based process. A comparison of substrate choices and considerations for R2R process integration is presented. A sensitive electrical method for evaluating the feasibility of R2R-based process integration schemes and materials selection is presented. MIM capacitor leakage, TFT device characteristics, NFC circuit performance, and defect density considerations are shown as a function of steel substrate bending, down to a diameter of 0.75 inches. Electrical characteristics and optical inspections show no measurable change to insulator characteristics, demonstrating a high degree of flexibility and overall device and process capability for R2R processing.

Polysilicon complementary metal oxide semiconductor (CMOS) thin film transistors (TFTs) are fabricated on large area, flexible stainless steel foils using novel ink depositions within a hybrid printed/conventional process flow. A self-aligned top gate TFT structure is realized with an additive materials approach to substitute the use of high capital cost ion implantation and lithography processes. Polyhydrosilane-based silicon ink is coated and laser crystallized to form the polysilicon channel. Semiconductor grade P-type and N-type unique dopant ink formulations are screen printed and combined with thermal drive in and activation to form self-aligned doped source and drain regions. A high refractory top gate material is chosen for its process compatibility with printed dopants, chemical resistance, and work function. Steel foil substrates are fully encapsulated to allow for high temperature processing. The resultant materials set and process flow enables TFT electrical characteristics with NMOS and PMOS mobilities exceeding 120 cm2/Vs and 60 cm2/Vs, respectively. On/Off ratios are >107. Reproducibility, uniformity, and reliability data in a production environmental is shown to demonstrate high volume, high throughput manufacturability. The device characteristics and scheme enable NFC (13.56MHz) capable circuits for use in flexible NFC and display-based smart labels and packaging.