This paper presents an ultra-low power wireless transceiver specialized for but not limited to medical implantable applications. It operates at the 402-405-MHz medical implant communication service band, and also supports the 420-450-MHz industrial, scientific, and medical band. Being IEEE 802.15.6 standard compliant with additional proprietary modes, this highly configurable transceiver achieves date rates from 11 kb/s to 4.5 Mb/s, which covers the requirements of conventional implantable applications. The phase-locked loop-based transmitter architecture is adopted to support various modulation schemes with limited power budget. The zero-IF receiver has programmable gain and bandwidth to accommodate different operation modes. Fabricated in 40-nm CMOS technology with 1-V supply, this transceiver only consumes 1.78 mW for transmission and 1.49 mW for reception. The ultra-low power consumption together with the 15.6-compliant performance in term of modulation accuracy, sensitivity, and interference robustness make this transceiver competent for various implantable applications.

Abstract:In this paper, a novel self-adjustable offset min-sum LDPC decoding algorithm is proposed for ISDB-S2 application. We present for the first time a uniform approximation of the check node operation through mathematical induction on Jacobian logarithm and theoretically shows that the offset value is mainly dependent on the difference of the two most unreliable inputs from the bit nodes, which makes the offset value adjustable during the iterative decoding procedure. Simulation results for all 11 code rates of ISDB-S2 demonstrate that the proposed method can achieve an average of 0.15 dB gain compared to the Min-sum based algorithms, and consumes only 1.21% computation complexity compared to BP-based algorithms in the best case. Keywords: LDPC decoding algorithm, ISDB-S2 Classification: Integrated circuits References[1] A. Hashimoto and Y. Suzuki, "A new transmission system for the advanced satellite broadcast," IEEE Trans.

Layered LDPC decoding algorithm is known to achieve high Bit Error Rate (BER) performance and high throughput for LDPC decoders. However, for ISDB-S2 (Integrated Services Digital Broadcasting via Satellite -Second Generation) LDPC decoder, applying layered algorithm directly will result in data conflict problem. In this paper, a novel selective recalculation method is proposed to solve the data conflict problem. It determines the inaccurately calculated values based on a recalculation decision rule, and correct them accordingly. By applying this selective recalculation method, the layered algorithm can achieve conflict free BER performance. Simulation results demonstrate that the proposed method can achieve 0.1dB gain for the code with most conflicts in ISDB-S2, under the same BER performance compared to the previous strategy to solve data conflict problem.

In this paper we propose an improved version of the charge transfer sense amplifier (CT sense amp) which completely compensates the threshold voltage (Vth) difference of MOS FETs.We also present a dual-Vth CMOS circuit scheme that enables high speed operation and low leakage power consumption at low supply voltage. A low-power, low-voltage 2k x 16b SRAM macro was designed and fabricated using a 0.25pm process. It showed stable operation with an access time of 7.0ns and power consumption of 3.9mW at 1 .OV (boost 1 SV), 100MHz, 85°C.

No abstract

No abstract

No abstract

No abstract