High-speed cascode sensing scheme for 1.0 V contact-programming mask ROM

Sasagawa, R.; Fukushi, I.; Hamaminato, Makoto; Kawashima, Seiichiro

doi:10.1109/vlsic.1999.797248

Cited by 19 publications

(5 citation statements)

References 1 publication

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“…The two popular embedded mask-programmed read only memories (ROM) of nanometer process NOR-ROM and NAND-ROM node. NOR-type logic-ROMs [2], [4] usually adopt high speed, small-capacity in the application. This metal-programmable NAND-ROM [5], [6] have a small cell area, lower power consumption, and NOR-type standby current than the smaller firmware.…”

Section: 2．mask-programmable Rommentioning

confidence: 99%

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The Study on Embedded Memory Circuit Design in Low-power SoC Chips for Mobile Systems

Ren¹,

Song-liang²,

Shao³

2012

IJACT

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The most important characteristic is a battery of mobile communication system with high performance, low power consumption and small size. Small form factor, and realize the system chips (SoC) and 3 D die-stacking (3 D-IC) method is to use multiple-chip instead of traditional solutions. Discusses the low voltage memory challenge created the circuit design and new memory solution and 3 D-IC mobile system chip (SoC) application. We explore new processor-memory architecture interface and the memory of the mobile and 3 D-IC SoC design.

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Section: 2．mask-programmable Rommentioning

confidence: 99%

“…Mobile system using nonvolatile memory (NVM) provides store programs and data in the power mode. The most commonly used NVM embedded logic-ROMs flash [1] and [2]- [6]. Clever use way can reduce the damage of the current system standby.…”

Section: Introductionmentioning

confidence: 99%

The Study on Embedded Memory Circuit Design in Low-power SoC Chips for Mobile Systems

Ren¹,

Song-liang²,

Shao³

2012

IJACT

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“…Novel sense amplifier The sense amplifier restores the signal full swing and compensates for the restricted fan-out-driving capability of the memory cell by accelerating the bit-line transition [13], [14]. A novel sense amplifier, which improves the signal transition time on bit-line with simple structure, is presented in our design.…”

Section: B the Address Decodersmentioning

confidence: 99%

Design of Small Area and Low Power Consumption Mask ROM

Cui

2007

2007 IEEE International Conference on Integrated Circuit Design and Technology

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The compact full custom layout design of a 16-Kb mask-programmable CMOS ROM with low power dissipation is introduced in this paper. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 PJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 um 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efriciently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, not only the layout design can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.

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“…Hence, the ROMs using the conventional SP approach still suffer the CIRF. An additional timing phase, resetting all the bitlines to ground (GND) after data-sensing phase, can eliminate the residual voltage in the SP approach at the expense of a timing penalty in the cycle time [1], [6], [21].…”

Section: Dvg3mentioning

confidence: 99%

A Full Code-Patterns Coverage High-Speed Embedded ROM Using Dynamic Virtual Guardian Technique

Chang

Chiou

Wen³

2006

IEEE J. Solid-State Circuits

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Crosstalk between bitlines induces read failure and limits the coverage of applicable code-patterns for high-speed contact/via-programming read-only memories (ROMs) in SoC. Owing to the variation in bitline loading across code-patterns, the amount of coupled noise on an accessed bitline is code-pattern-dependent. This crosstalk effect worsens, with larger coupling capacitance and smaller intrinsic loading, as the technology node shrinks. This study proposes dynamic virtual guardian (DVG) techniques for contact/via-programming ROM macros and compilers to eliminate the crosstalk-induced read failure and increase the code-patterns coverage. Compared with conventional ROMs, DVG techniques achieve higher speed, lower power consumption and better design for manufacturing (DFM) capability with full code-patterns coverage. Experiments on fabricated designs, a conventional ROM and two 256 Kb DVG ROMs, using 0.18 m 1P5M CMOS technology have demonstrated that DVG techniques achieve 100% code-pattern coverage under a small sensing margin.

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High-speed cascode sensing scheme for 1.0 V contact-programming mask ROM

Cited by 19 publications

References 1 publication

The Study on Embedded Memory Circuit Design in Low-power SoC Chips for Mobile Systems

The Study on Embedded Memory Circuit Design in Low-power SoC Chips for Mobile Systems

Design of Small Area and Low Power Consumption Mask ROM

A Full Code-Patterns Coverage High-Speed Embedded ROM Using Dynamic Virtual Guardian Technique

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