A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's

Kawashima, S.; Mori, Toshihiko; Sasagawa, R.; Hamaminato, Makoto; Wakayama, S.; Sukegawa, K.; Fukushi, I.

doi:10.1109/4.668995

Cited by 17 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…And, divided bit lines of local and global bit lines could achieve higher speed at the expense of larger area. Figure 5 shows a Balanced Charge-transfer Sense Amplifier (BCTSA) [15]. This paper first adopted the BCTSA to SRAM, which had been studied for DRAM application.…”

Section: Voltage-mode Sense Amplifiersmentioning

confidence: 99%

“…The charge-transfer SA was proposed in 1976, which consists of a pair of NMOS transistors [13]. Subsequently, several SA designs have been proposed utilizing the same charge-transfer mechanism [14][15][16], all of which exhibit a fast response speed, almost independent of the bit line capacitance. However, the charge-transfer SA usually requires an intermediate voltage and complicated control signals increasing the additional area and energy.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Review of Sense Amplifiers for Static Random Access Memory

Zhu¹,

Bai²,

Wu³

2013

IETE Tech Rev

View full text Add to dashboard Cite

Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs). This paper provides a systematic overview of voltage-mode, charge-transfer, current-mode SAs, and calibration-based SAs for SRAM. Recent advances in developing SAs have paved the way for lower delay, lower energy, and higher reliability. For comparison, all SAs based on 65 nm CMOS technology are simulated under different power supplies, bit-line capacitances, and various process corners. When the bit-line capacitance is 50 fF, charge-transfer and current-mode SAs are about 40% faster than voltage-mode SAs, and the energy consumption of charge-transfer SA is 30% lower than that of other voltage-mode SAs. Delay and energy of HCI-trimming SA and multi-sized SA are about equal to that of voltage-mode SAs. Because of low bit-line precharged voltage, the energy of charge-limited sequential SA (CLSSA) is 64% lower than that of charge-transfer SA, while the delay of CLSSA is five times larger than the other SAs. AUTHORSJiafeng Zhu received the M.S. degree from Southeast University, China, in 2010 in electronic engineering. He is currently a Ph.D. candidate in National ASIC System Engineering Research Center, Southeast University, China. His research interests include high performance and low power SRAM design and mix-signal IC design.

show abstract

Section: Voltage-mode Sense Amplifiersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Review of Sense Amplifiers for Static Random Access Memory

Zhu¹,

Bai²,

Wu³

2013

IETE Tech Rev

View full text Add to dashboard Cite

show abstract

“…In our implementation, the write data-bus capacitance was about twice as large as the bit-line capacitance. To achieve capacitance matching, we employed the two-to-four encoding technique proposed in [19]. Every two bits of data is encoded as a onehot-out-of-four signal.…”

Section: Reducing the Write Powermentioning

confidence: 99%

Low-power SRAM design using half-swing pulse-mode techniques

Mai

Mori

Amrutur³

et al. 1998

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, and bit lines. Charge recycling between positive and negative half-swing pulses further reduces the power dissipation. These techniques are demonstrated in a 2-K 2 2 2 16-b SRAM fabricated in a 0.25-m dual-Vt Vt Vt CMOS technology that dissipates 0.9 mW operating at 1 V, 100 MHz, and room temperature. On-chip voltage samplers were used to probe internal nodes.

show abstract

“…What must be avoided are more complex sense-amps whose aim is to improve response time and/or lower energy consumption for a fixed V DD , but fail for varying V DD . One example is a chargetransfer sense-amp [5].…”

Section: Sense Amp Designmentioning

confidence: 99%

Design issues for Dynamic Voltage Scaling

Burd¹,

Brodersen²

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

152

View full text Add to dashboard Cite

Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the processor's supply voltage so that it consumes the minimal amount of energy by operating at the minimum performance level required by the active software processes. A dynamically varying supply voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability.

show abstract

A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's

Cited by 17 publications

References 12 publications

Review of Sense Amplifiers for Static Random Access Memory

Review of Sense Amplifiers for Static Random Access Memory

Low-power SRAM design using half-swing pulse-mode techniques

Design issues for Dynamic Voltage Scaling

Contact Info

Product

Resources

About