A novel polymeric bottom anti-reflective coating (PARC) process has been developed for O.25tm Flash device on the severe topology with KrF lithography. The refractive index, n, and the extinction coefficient, k, of PARC can be tuned to match the optical properties of substrates. The CD uniformity range within wafer is O.O27m and the variation is O.OO7tm for the polymer BARC. However, the data from organic ARC is O.O47tm and O.O24tm for the CD uniformity and variation, respectively. The PARC is a uniform and conformal layer of thin film, which significantly improves the CD uniformity of critical layers such as poly Si gate and other features over topography. Since PARC is a highly conformal film, it can be deposited very uniformly across topography. The thickness of PARC is very uniform on the poly Si/TEOS oxide stack of polysilicon gate of a O.25im Flash device with highly topology. In contrast, the thickness of BARC varies from place to place. While the thickness of BARC is very thick in the trough, it becomes quite thin at the top. Such a variation not only decreases the photo process latitude, but also creates a problem for the etch process. Furthermore, the etching rate of PARC is about 200% higher than BARC, so that there is less resist loss during BARC open step.
A novel dual layer polymeric anti-reflective coating (PARC) process has been developed for sub-O.l8jtm KrF lithography. The refractive index, n, and the extinction coefficient, k, of PARC can be tuned to match the optical properties of various substrates. The PARC is a uniform and conformal layer of thin film, which significantly improves the CD uniformity of critical layers such as polysilicon gate and other features over the severe topography. However, the high k PARC has scum issue near the edge of 0.18 m polysilicon line. Some unknown active chemical reaction occurs when high k PARC is directly adhered to the photoresist. The process window is much improved after insertion of a layer of lower k PARC between photoresist and the polysilicori film. With the process simulation, the optimized dual layer of PARC are stacked with 300A of lower k (0.161) and 300A ofhigher k (0.351). However, the process window from the simulation is quite small, the reflectivity ofless than 2% has only for both k values of PARC. The forming rate of the PARC could be controlled to as low as 4.3A per second and with very good film uniformity of less than 5%. We then process the dual layer of PARC on 2500A polysilicon film with 27A gate oxide, a O.8im DOF of process window is obtained for 0. l8tm polysilicon gate line. All the scum near the edge of polysilicon gate line is disappeared with the new dual layer PARC process.
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