The superior carrier mobility of SiGe alloys make them a highly desirable channel material in complementary metal-oxide-semiconductor (CMOS) transistors. Passivation of the SiGe surface and the associated minimization of interface defects between SiGe channels and high- k dielectrics continues to be a challenge for fabrication of high-performance SiGe CMOS. A primary source of interface defects is interfacial GeO . This interfacial oxide can be decomposed using an oxygen-scavenging reactive gate metal, which nearly eliminates the interfacial oxides, thereby decreasing the amount of GeO at the interface; the remaining ultrathin interlayer is consistent with a SiO -rich interface. Density functional theory simulations demonstrate that a sub-0.5 nm thick SiO-rich surface layer can produce an electrically passivated HfO/SiGe interface. To form this SiO -rich interlayer, metal gate stack designs including Al/HfO/SiGe and Pd/Ti/TiN/nanolaminate (NL)/SiGe (NL: HfO-AlO) were investigated. As compared to the control Ni-gated devices, those with Al/HfO/SiGe gate stacks demonstrated more than an order of magnitude reduction in interface defect density with a sub-0.5 nm SiO -rich interfacial layer. To further increase the oxide capacitance, the devices were fabricated with a Ti oxygen scavenging layer separated from the HfO by a conductive TiN diffusion barrier (remote scavenging). The Pd/Ti/TiN/NL/SiGe structures exhibited significant capacitance enhancement along with a reduction in interface defect density.

Suppression of electronic defects induced by GeO x at the high-k gate oxide/SiGe interface is critical for implementation of high mobility SiGe channels in CMOS technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO xrich interlayer on SiGe. Experimental studies in literature indicates better interface formation with Al 2 O 3 in contrast to HfO 2 on SiGe however the mechanism behind this is not well understood. In this study, the mechanism of forming a low defect density interface between Al 2 O 3 /SiGe is investigated using atomic layer deposited (ALD) Al 2 O 3 insertion into or on top of ALD HfO 2 gate oxides. To elucidate the mechanism, correlations are made between the defect density determined by impedance measurements and the chemical and physical structure of the interface determined by high resolution scanning transmission electron microscopy and electron energy loss spectroscopy (STEM-EELS). Compositional analysis reveals an SiO x rich interlayer for both Al 2 O 3 /SiGe and HfO 2 /SiGe interfaces with insertion of Al 2 O 3 into or on top of the HfO 2 oxide. The data is consistent with the Al 2 O 3 insertion inducing decomposition of the GeO x from the interface to form an electrically passive, SiO x rich interface on SiGe. This mechanism shows that nanolaminate gate oxide chemistry cannot be interpreted as resulting from a simple layer by layer ideal ALD process because the precursor or its reaction products can diffuse though the oxide during growth and react at the semiconductor interface. This result shows that in scaled CMOS, remote oxide ALD (oxide ALD on top of the gate oxide) can be used to suppress electronic defects at gate-oxide semiconductor interfaces by oxygen scavenging.

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