The superior carrier mobility of SiGe alloys make them a highly desirable channel material in complementary metal-oxide-semiconductor (CMOS) transistors. Passivation of the SiGe surface and the associated minimization of interface defects between SiGe channels and high- k dielectrics continues to be a challenge for fabrication of high-performance SiGe CMOS. A primary source of interface defects is interfacial GeO . This interfacial oxide can be decomposed using an oxygen-scavenging reactive gate metal, which nearly eliminates the interfacial oxides, thereby decreasing the amount of GeO at the interface; the remaining ultrathin interlayer is consistent with a SiO -rich interface. Density functional theory simulations demonstrate that a sub-0.5 nm thick SiO-rich surface layer can produce an electrically passivated HfO/SiGe interface. To form this SiO -rich interlayer, metal gate stack designs including Al/HfO/SiGe and Pd/Ti/TiN/nanolaminate (NL)/SiGe (NL: HfO-AlO) were investigated. As compared to the control Ni-gated devices, those with Al/HfO/SiGe gate stacks demonstrated more than an order of magnitude reduction in interface defect density with a sub-0.5 nm SiO -rich interfacial layer. To further increase the oxide capacitance, the devices were fabricated with a Ti oxygen scavenging layer separated from the HfO by a conductive TiN diffusion barrier (remote scavenging). The Pd/Ti/TiN/NL/SiGe structures exhibited significant capacitance enhancement along with a reduction in interface defect density.
Silicon germanium (SiGe) is a multi-functional material considered for quantum computing, neuromorphic devices and CMOS transistors. However, implementation of SiGe in nano-scale electronic devices necessitates suppression of surface states dominating on electronic properties. The absence of a stable and passive surface oxide for SiGe results formation of charge traps at the SiGe -oxide interface induced by GeO x . In an ideal ALD process in which oxide is grown layer-by-layer, the GeO x formation should be prevented with selective surface oxidation (i.e. formation of an SiO x interface) by controlling oxidant dose in first few ALD cycles of the oxide deposition on SiGe. However, in a real ALD process, the interface evolves during entire ALD oxide deposition due to diffusion of reactant species through the gate oxide. In this work, this diffusion process in non-ideal ALD is investigated and exploited: the diffusion through the oxide during ALD is utilized to passivate the interfacial defects by employing ozone as a secondary oxidant. Periodic ozone exposure during gate oxide ALD on SiGe is shown to reduce the integrated trap density (D it ) across the band gap by nearly an order of magnitude in Al 2 O 3 (< 6×10 10 cm -2 ) and in HfO 2 (< 3.9×10 11 cm -2 ) by forming a SiO x rich interface on SiGe. Depletion of Ge from the interfacial layer (IL) by enhancement of volatile GeO x formation and consequent desorption from the SiGe with ozone insertion during ALD growth process is confirmed by electron energy loss spectroscopy (STEM-EELS) and hypothesized to be the mechanism for reduction of the interfacial defects. In this work, the nanoscale mechanism for defect suppression at SiGe oxide interface is demonstrated which is engineering of diffusion species in ALD process due to facile diffusion of reactant species in non-ideal ALD.
Silicon germanium (SiGe) channels for CMOS are favorable due to high intrinsic carrier mobility and band gap tunability[1] To utilize the superior properties of SiGe, low interface defect density (Dit) must be obtained at the SiGe-high k interface. Germanium oxide (GeOx) is the primary source of interface defects[2]. In comparison with GeOx, SiOx has a higher heat of formation. Using this difference, it is possible to reduce interface defects with selective reduction or diffusion of GeOx by employing an oxygen-scavenging metal as a gate material[4,5] such as aluminum. ALD was performed with TDMAH and H2O to grow 50 cycles (5nm) of HfO2 at 250C. 50 nm thick, 150 um diameter Ni or Al gate metal was deposited by thermal evaporation. C-V measurement were employed to characterized the electronic defects. The interface trap density (Dit) integrated across the band gap was more than an order of magnitude lower for Al vs Ni gated MOSCAPs. From TEM-EELS-EDS measurement, Al gated MOSCAPs were observed to have a very thin interfacial oxide layer (<0.5 nm) with high-k oxide atoms almost directly bonded with the SiGe surface atoms with just a thin SiOx interlyer. Selective scavenging of Ge-O vs Si-O bonds is consistent with a DFT model showing HfO2/SiOx/SiGe interfaces can be defect-free. DFT models also show that two 3- and 5-fold coordinated interfacial Si atoms do not create any mid-gap or band-edge states. These results indicate the need to form a SiOx interface between HfO2 and SiGe, but the same interface may be created with other techniques. The alternative techniques include a selective oxidation of SiGe form SIOx using remote O3 oxidation and ALD of an Si rich layer on SiGe. The key issue is which of the three techniques is manufacturable and can produce both a scale oxide and scaled interlayer. [1] Liu, C. et. al, MRS Bull. 39, 658–662 (2014). [2] Zhang, L. et al, ACS Appl. Mater. Interfaces 8, 19110–19118 (2016). [3] Zhang, L. et al, ACS Appl. Mater. Interfaces 7, 20499–20506 (2015). [4] Kim, H. et al, J. Appl. Phys. 96, 3467–3472 (2004). [5] Frank, M. et al, ECS Solid State Lett. 2, N8–N10 (2012). [6] Sardashti, K. et al. Appl. Surf. Sci. 366, 455–463 (2016)
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