The automatic generation of tests for combinational digital circuits is examined from the standpoint of a guided search through a search space. The limitations of this process, namely the size of the search space and the overall strategy, are identified and methods are presented to reduce the size of the search space as well as produce a more optimal ordering of node assignments. A new algorithm is proposed that uses the smaller search space and the improved ordering for node assignments based on a topological analysis of the circuit. Results are presented indicating that this new algorithm, termed TOPological Search (TOPS), is faster than existing algorithms and also rapidly identifies many redundant faults without search. optional assignment nodes do not have a unique requir$d value. For example, all tests for a stuck fault mandate that a difference be produced at the fault site between the good value and the faulty value. This assignment is notl a matter of choice and is therefore, a mandatory assignment. On the other hand, if more than one path exists for obsertving: the difference at the circuit outputs, some choice must be made as to which path or set of paths to use; s&h choices lead to optional assignments.
IntroductionThe generation of tests for combinational digital circuits can be characterized as a search problem. A test for a fault can be found by trying different patterns until one is found that differentiates the good circuit from the faulty circuit. Finding an efficient way to try these different patterns makes the problem amenable to search techniques [Kirkland 871. The search space can be quite large, however, and a solution may not exist. Some method must be used to organize the search process to assure that every possible pattern can be tried and that no pattern is tried twice. It is not necessary, however, to explicitly search the entire space; it may be possible in some cases to determine that no' solution exists with only a partial search [Gael 811. Similarly, if a way can be found to search a smaller space for the solution, the size of the search problem is reduced and the test generation problem becomes more tractable.
Recognizing that the delay of a circuit is extremely sensitive t o manufacturing process variations, this paper proposes a methodology for statistical timing analysis. We present a triple-node delay model which inherently captures the effect of input transition time on the gate delays. Response Surface Methods are used so that the statistical gate delays are generated efficiently. A new path sensitization criterion based on the minimum propagatable pulse width (MPPW) of the gates along a path is used to check for false paths. The overlap of a path with longer paths determines its "statistical significance" t o the overall circuit delay. Finally, the circuit delay probability density function is computed by performing a Monte Carlo simulation on the statistically significant path set.
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